3D-IC 封裝鎳/銦及鎳/錫凸塊接合界面研究

Abstract

近年來為了滿足人類在生活上的各式需求,電子產品的功能日益複雜化,使得半導體的製程技術不斷地精進,電晶體的尺寸也因此不斷的縮小。隨著電晶體的尺寸不斷的縮小,微影技術的發展將趨於困難,此外,量子效應也會越趨顯著。有鑑於此,透過3D-IC 技術晶片的堆疊,讓不同功能的積體電路整合在一起,是一個大有可為且前瞻性的方法。然而,3D-IC 技術的可靠度問題是值得關心與評估的。 本研究即是針對3D-IC 技術晶片的堆疊接合介面的研究,來提供3D-IC 技術在可靠度上面的參考。本研究分為兩部份:第一部份為利用固液擴散接合的方法來針對晶片堆疊接合界面所產生的孔洞,利用銀的介金屬來填補另一介金屬所產生的孔洞,使得可靠度大幅度的提升。第二部份為利用銦做為矽晶片堆疊的中間層,使得極低溫接合成為可能。 本研究的第一部分結果顯示利用銀的介金屬化合物,可有效的填補其他金屬的介金屬化合物因其扇貝狀的結構所導致的孔洞,使得接點強度大幅度的上升。本研究的第二部份結果顯示利用銦做為矽晶片堆疊的中間層,雖然可在極低的溫度完成矽晶片的堆疊,但其所引發的銦鬚問題卻會產生矽晶片中的電路短路,其生長的速率隨著溫度升高而變快,生長的長度、寬度和數目隨著時間而變長、變寬和變多。

In order to fulfill every demand in life for human beings in these years, the functions of electronic products have been complicated day by day such that the manufacture technology of semiconductor is improved at every moment and the size of transistor is become smaller and smaller. Owing to transistor is smaller and smaller, developing photolithography technology has become more difficult ever since. In addition, quantum phenomenon is conspicuous when the size of transistor is small enough. Due to these several reasons, 3D-IC technology for chip stacking to integrate chips with different function is promising and foresighted way to overcome these difficulties as mentioned above. This research is primarily focus upon the bonding interfaces of chip stacking in 3D-IC technology to provide better performance in reliability issues. This research is divided into two parts. The first part is to use silver-contained intermetallic compounds to eliminate voids via solid-liquid interdiffusion bonding technique for chips stacking and hence the reliability is improved drastically. The second part is to use indium as interlayer for silicon chip stacking such that extremely low temperature bonding turns into possibility. The results of this research in first part indicated that the use of silver-contained intermetallic compounds is an effective way to fill up the voids which are created due to scallop shape of other metal-contained intermetallic compounds. Thus, the strength of the bonding is increased dramatically. The results of this research in second part indicated that the silicon chips can be bonded by using indium as interlayer at extremely low temperature. It will induce indium whisker to short circuits in silicon chip, however. Also, the growth velocity of indium whisker is faster, longer, wider and the number of indium whisker is increased as the working temperature of silicon chip is increased.