微波多層被動電路之佈局對電路檢查前、後段整合

Abstract

本篇論文提出了一種將電路佈局圖轉換成電路表時，產生各個元件連接狀態的方法。設計者所設計出來的佈局圖，會以GDSII的檔案格式儲存。接著進行矩形切割，切割出來的矩形會再使用各種原則判斷每個矩形代表的電容或電感。論文中主要針對擷取出來的電感或電容之間的連接狀況加以處理，利用多邊形的分群可以找到同層元件之間的連接，在跨層的元件連接中我們使用貫穿孔來連接不同層的元件。我們還需要加入各元件自己的連結點，以標示出元件的兩個端點，經由共同的連結點可以產生有連結狀態的網路表。最後我們就可以把電路佈局圖轉換成網路表來進行與電路圖網路表的比對。

This thesis presents a method that can generate connection status of each component and transform circuit layout into circuit netlist. The circuit layout designed by designer will be stored in format of GDII. Then dividing the rectilinear shape in layout into rectangles that may constitute capacitors and inductors. With clustering of polygon, we can find connection of each component on same layer. In different layer, we use vias to connect components on different layers. Then we add connecting nodes of each component, to mark two endpoints of each component. By way of common connect node we can generate netlist of connection. Finally we can transform circuit layout to netlist to compare with schematic netlist.