應用於IEEE 802.11a之突波抑制頻率合成器

Abstract

在無線通訊系統中，本地振盪器(local oscillator)扮演很重要的角色。在射頻收發機中，其所使用的本地振盪器通常是內嵌於鎖相迴路系統中，以達成穩定與精確之頻率輸出，此系統即為頻率合成器。而在射頻系統中，頻率合成器的設計仍然是最富挑戰性的議題之一。因為它必須要達到非常嚴苛的要求，例如：鎖定時間(settling time)、相位雜訊(phase noise)、參考突波(reference spur)等。為了在這些要求中取得一個適當的折衷方案，我們提出了一個新的架構，採用高解析度(high-resolution)相位誤差校正電路及自動頻率控制(automatic frequency control)電路，來達到一個快速鎖定、寬頻操作和低參考突波的鎖相迴路。 為了滿足位於5 GHz頻帶之IEEE 802.11a無線區域網路的標準，一個雙頻帶鎖相迴路型頻率合成器在台積電零點一八微米互補金氧半製程環境下設計並且製作完成。晶片的面積大小為零點九二毫米乘於零點八三毫米。在5.76 GHz輸出頻率下，當高解析度相位誤差校正電路開啟之後，量測所得的輸出突波位準低於-63 dBc。對所有的輸出頻率範圍而言，校正後所量測到的參考突波位準，較校正前降低了5.6至6.7 dB。此頻率合成器在使用一點八伏特供應電壓的情形下，電流消耗為十六毫安培；而量得的相位雜訊在1 MHz的偏移頻率下，為-104 dBc/Hz。

In wireless communication systems, the local oscillator (LO) plays an important role. The oscillator used in a RF transceiver is usually embedded in a phase-locked loop (PLL) system so as to achieve a stable and precise definition of the output frequency, and this system is called “frequency synthesizer”. Synthesizer design still remains one of the most challenging issues in RF systems because it must meet very stringent requirements such as: settling time, phase noise, reference spur, etc. To reach an appropriate compromise among these requirements, we have proposed a new architecture adopting the high-resolution phase error calibration circuits and automatic frequency control (AFC) circuits to achieve a fast locking, wide range, and low reference spur PLL. To satisfy the IEEE 802.11a WLAN standards in the 5 GHz bands, a dual-band PLL-based frequency synthesizer is designed and fabricated in TSMC 0.18-μm CMOS technology. The chip size is 0.92 mm × 0.83 mm. At 5.76 GHz, the measured output spur level is less than -63 dBc after the high-resolution phase error calibration circuits are active. Throughout the whole output frequency range, the measured reference spurs are suppressed by 5.6-6.7 dB with calibration. The synthesizer draws 16 mA from a 1.8-V power supply, and the measured phase noise is -104 dBc/Hz at an offset frequency of 1 MHz.