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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎 | |
| dc.contributor.author | Tzu-Hsiang Lin | en |
| dc.contributor.author | 林子翔 | zh_TW |
| dc.date.accessioned | 2021-05-12T09:34:53Z | - |
| dc.date.available | 2018-10-12 | |
| dc.date.available | 2021-05-12T09:34:53Z | - |
| dc.date.copyright | 2018-10-12 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-10-03 | |
| dc.identifier.citation | [1] T. H. Li. (2017). A Flexible Hybrid Fault Simulator for Software-Based Self-Test (Unpublished master’s thesis). National Taiwan University, Taipei, Taiwan.
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Reorda, 'A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions,' 26th IEEE VLSI Test Symposium (vts 2008), San Diego, CA, 2008, pp. 389-394. [15] F. Corno, E. Sanchez, M. S. Reorda and G. Squillero, 'Automatic Test Program Generation: A Case Study,' in IEEE Design & Test of Computers, vol. 21, no. 2, pp. 102-109, Mar-Apr 2004. [16] D. Sabena, M. S. Reorda and L. Sterpone, 'On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 4, pp. 813-823, April 2014. [17] Y. Zhang, H. Li and X. Li, 'Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 7, pp. 1220-1233, July 2013. [18] J. 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Ali, 'Automatic Generation of Test Instructions for Path Delay Faults Based-On Stuck-At Fault in Processor Cores Using Assignment Decision Diagram,' 2014 5th International Conference on Intelligent and Advanced Systems (ICIAS), Kuala Lumpur, 2014, pp. 1-5. [30] N. Hage, R. Gulve, M. Fujita and V. Singh, 'On Testing of Superscalar Processors in Functional Mode for Delay Faults,' 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 397-402. [31] G. Ayers, A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. (Old University of Utah XUM archieve), 2014, from https://github.com/grantae/mips32r1_xum | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/handle/123456789/1248 | - |
| dc.description.abstract | 由於傳統結構性測試的不足，應用軟體自我測試(software-based self-test)成為了非侵入性、功能性以及全速測試的替代方案。應用軟體自我測試的技術可彌補傳統結構性測試的不足，並且能在客戶使用階段提升硬體可靠性(reliability)。在論文中，我們建立了一套完整的應用軟體測試流程，其中包含非功能性測試限制提取、測試圖騰指令轉換器、測試程式產生器、電路錯誤模擬器。此外，為了確保所產生測試程式之測試品質，我們亦提供了隨機程式評估比較結果於文末。
我們所提出的應用於軟體測試流程目的為在程式或應用執行的過程中，偵測出可能發生的電路老化缺陷(aging defect)及錯誤。所使用的錯誤模型為電路老化效應(aging effect)所造成的硬體缺陷，我們將模擬因電路老化效應所造成的路徑延遲錯誤(path delay fault)及轉態延遲錯誤(transition delay fault)，以偵測電路老化效應的初期現象。 | zh_TW |
| dc.description.abstract | Since the insufficient of conventional structural test, software-based self-test becomes the alternative solution for a non-intrusive, functional and at-speed testing. The use of software-based self-test could compensate the shortages of conventional structural test and enhance the hardware in-field reliability. In the thesis, we have provided a complete test flow for software-based self-test including constraint extraction, pattern-to-instruction converter, test program generator and fault simulator. Besides, in order to confirm the quality of test program generated by our methodology, the results of random program evaluation have been displayed in the last part of this thesis.
The proposed software-based self-test methodology aims to detect the possible hardware faults during the execution of test programs or applications. The target fault model is the hardware fault caused by aging effect. We model the fault behavior as the path delay fault and transition delay fault models for aging fault simulation. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-12T09:34:53Z (GMT). No. of bitstreams: 1 ntu-107-R05943090-1.pdf: 5103002 bytes, checksum: 03bc47c7f3e0c3d871774de1a543f272 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Motivation 2 1.1.1 Challenges of manufacturing testing 2 1.1.2 Software-based self-test 3 1.1.3 Challenge of software-based self-test 5 1.2 Review of Previous Techniques 6 1.2.1 Test program generation approaches 6 1.2.2 Fault injection approaches 7 1.3 Contribution 9 1.4 Organizations of the Thesis 10 Chapter 2 Aging Effect and Delay Fault Testing 11 2.1 Aging Effect 12 2.2 Delay Fault Testing 12 2.3 Software-Based Delay Fault Testing 15 2.3.1 Path activation monitoring 16 2.3.2 Fault injection and detection 21 Chapter 3 Proposed Method for Software-Based Self-Test on Delay Defects 24 3.1 Proposed Methodology 25 3.2 Pre-Processing 25 3.3 Test generation 28 3.3.1 Static timing analysis 29 3.3.2 Automatic test pattern generation (ATPG) 30 3.3.3 Pattern-to-instruction converter 32 3.4 Fault Simulation 37 Chapter 4 Experiment Result 39 4.1 Experiment Setup 40 4.2 Result Statistics 43 4.2.1 Transition delay fault testing 43 4.2.2 Path delay fault testing 44 4.2.3 Random program evaluation 46 Chapter 5 Conclusion 54 REFERENCE 56 | |
| dc.language.iso | en | |
| dc.subject | 應用軟體自我測試 | zh_TW |
| dc.subject | 積體電路系統測試 | zh_TW |
| dc.subject | 系統可靠性 | zh_TW |
| dc.subject | 電路老化效應 | zh_TW |
| dc.subject | Aging Effect | en |
| dc.subject | VLSI System Testing | en |
| dc.subject | Reliability | en |
| dc.subject | Software-Based Self-Test | en |
| dc.title | 應用於軟體自我測試之電路老化缺陷偵測 | zh_TW |
| dc.title | Software-Based Self-Test for Aging Defect Detection | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂學坤,李進福,黃炫倫 | |
| dc.subject.keyword | 應用軟體自我測試,電路老化效應,系統可靠性,積體電路系統測試, | zh_TW |
| dc.subject.keyword | Software-Based Self-Test,Aging Effect,Reliability,VLSI System Testing, | en |
| dc.relation.page | 60 | |
| dc.identifier.doi | 10.6342/NTU201803476 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2018-10-04 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-107-1.pdf | 4.98 MB | Adobe PDF | 檢視/開啟 |
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