相容於低溫後段製程之P型SnO薄膜電晶體硫化技術開發與特性研究

Abstract

本論文主要開發具備低溫後段製程相容性的p型氧化亞錫（SnO）薄膜電晶體，目標是開發可應用於單體三維積體電路的p型氧化物元件，滿足低溫製程、低功耗操作與高密度整合的需求。SnO具有本質p型導電特性，且價帶頂由Sn 5s與 O 2p 軌域混成形成，具有較佳的電洞傳輸能力。但是SnO薄膜容易受到缺陷態與較高背景電洞濃度影響，導致元件漏電流偏高與穩定性受限。所以本研究導入CVD 硫化後處理技術，藉由硫元素對SnO通道進行摻雜，來降低缺陷相關漏電路徑並提升元件電性與可靠度。 本研究成功利用CVD系統對SnO TFT進行硫化後處理。實驗結果顯示，本研究所製作的留話條件可在230°C的低溫條件進行製程，本實驗硫化條件可使SnO TFT 的off current降低約兩個數量級，on/off current ratio提升約1–2個數量級，並改善次臨界擺幅，顯示硫化處理能有效抑制漏電流也可以提升閘極控制能力。此改善是因為硫元素導入後，與SnO薄膜中的缺陷或未飽和鍵結反應，減少缺陷輔助的漏電路徑。此外，也有透過XPS、XRD與TEM等材料分析方法確認硫化後薄膜之化學鍵結、晶體結構與截面形貌。 在可靠度分析方面，也透過正偏壓應力與負偏壓應力測試評估硫化處理對元件穩定性的影響。由結果顯示硫化後SnO TFT相較於pristine元件有較小的臨界電壓漂移，表示硫化處理可降低偏壓操作下的缺陷捕捉效應，去提升元件穩定性。也可以確定硫化後元件在長時間偏壓應力下，仍可維持較穩定的臨界電壓與關態電流表現，並比pristine元件有較佳的長時間操作穩定性與耐久度。 綜合以上結果，本研究成功開發出一套相容於低溫後段製程之p型SnO TFT 製程，並證明CVD硫化處理可有效改善SnO TFT的漏電流、開關特性、次臨界擺幅與偏壓穩定性。未來希望透過本製程具備低溫與後段整合相容的優勢，可進一步應用於低功耗 CMOS 元件及 Monolithic 3D IC 之垂直整合架構，作為發展 p 型氧化物半導體元件的可行方案。

This thesis focuses on the development of low-temperature BEOL-compatible p-type SnO thin-film transistors for monolithic 3D integrated circuits. SnO is a promising p-type oxide semiconductor due to its intrinsic p-type conductivity and favorable hole transport properties. However, defect states and high background hole concentration in SnO thin films lead to high leakage current and limited stability. Therefore, we used CVD sulfurization post-treatment to modify the SnO channel, reduce defect-related leakage paths, and improve device performance and reliability. In this study, SnO TFTs were successfully sulfurized using CVD system at a low temperature of 230 °C. After sulfurization, the off current was reduced by approximately two orders, the on/off current ratio was improved by about 1–2 orders, and the subthreshold swing was enhanced. These improvements indicate that sulfurization effectively suppresses defect-related leakage paths and improves gate control. We also used XPS, XRD, and TEM analyses to confirm the chemical bonding, crystal structure, and cross-sectional morphology of the sulfurized SnO thin films. For reliability analysis, positive and negative bias stress tests were performed to evaluate device stability. The sulfurized SnO TFTs showed a smaller threshold voltage shift than the pristine devices, indicating that sulfurization can reduce defect trapping under bias stress. In addition, the sulfurized devices maintained more stable threshold voltage and off-current characteristics during long-term operation. These results confirm that sulfurization effectively improves the reliability and stability of SnO TFTs. Overall, this study successfully developed a low-temperature BEOL-compatible p-type SnO TFT process. The results show that CVD sulfurization can effectively reduce leakage current, improve switching characteristics and subthreshold swing, and enhance bias stability. Therefore, this process shows potential for low-power CMOS devices and vertically integrated Monolithic 3D IC applications, offering a feasible approach for the development of p-type oxide semiconductor devices.