請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103699完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳志毅 | zh_TW |
| dc.contributor.advisor | Chih-I Wu | en |
| dc.contributor.author | 黃冠瑜 | zh_TW |
| dc.contributor.author | Kuan-Yu Huang | en |
| dc.date.accessioned | 2026-08-19T16:06:37Z | - |
| dc.date.available | 2026-08-20 | - |
| dc.date.copyright | 2026-08-19 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-08-05 00:00:00 | - |
| dc.identifier.citation | [1]K. Dhananjay, P. Shukla, V. F. Pavlidis, A. Coskun, and E. Salman, “Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 68, no. 3, pp. 837–843, Mar. 2021.
[2]T.-C. Chiang et al., “P-Type SnO Thin-Film Transistor With Scaled Channel Lengths for High-Density Monolithic Integration in Complementary Logic Circuits Applications,” IEEE Electron Device Lett., vol. 46, no. 5, pp. 769–772, May 2025. [3]G. E. Moore, "Cramming more components onto integrated circuits," Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, 1998. [4]S. Thuries et al., “M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC,” in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar. 2020, pp. 1740–1745. [5]J. E. Lilienfeld, “Method and apparatus for controlling electric currents,” U.S. Patent 1745175, Jan. 28, 1930. [6]J. E. Lilienfeld, “Device for controlling electric current,” U.S. Patent 1900018, Mar. 7, 1933. [7]E. Fortunato, P. Barquinha, and R. Martins, “Oxide Semiconductor Thin-Film Transistors: A Review of Recent Advances,” Adv. Mater., vol. 24, no. 22, pp. 2945–2986, 2012. [8]C. Fenouillet-Beranger et al., “FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration,” Solid-State Electron., vol. 113, pp. 2–8, Nov. 2015. [9]S. Datta, S. Dutta, B. Grisafe, J. Smith, S. Srinivasa, and H. Ye, “Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration,” IEEE Micro, vol. 39, no. 6, pp. 8–15, Jan. 2019. [10]M. Choe et al., “Stabilization of top-gate p-SnO transistors via ultrathin Al2O3 interlayers for hysteresis-free operation,” J. Mater. Chem. C, vol. 13, no. 24, pp. 12308–12316, Jun. 2025. [11]S. H. Kim et al., “Fabrication of high-performance p-type thin film transistors using atomic-layer-deposited SnO films,” J. Mater. Chem. C, vol. 5, no. 12, pp. 3139–3145, 2017. [12]K. A. Aabrar et al., “Improved Reliability and Enhanced Performance in BEOL Compatible W-doped In2O3 Dual-Gate Transistor,” in 2023 International Electron Devices Meeting (IEDM), Feb. 2023, pp. 1–4. [13]D. P. Heineck, B. R. McFarlane, and J. F. Wager, “Zinc Tin Oxide Thin-Film-Transistor Enhancement/Depletion Inverter,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 514–516, May 2009. [14]Y. Ogo et al., “p -channel thin-film transistor using p-type oxide semiconductor, SnO,” Appl. Phys. Lett., vol. 93, no. 3, p. 032113, Jul. 2008. [15]S.-Y. Ahn, S. C. Jang, A. Song, K.-B. Chung, Y. J. Kim, and H.-S. Kim, “Performance enhancement of p-type SnO semiconductors via SiOx passivation,” Mater. Today Commun., vol. 26, p. 101747, Mar. 2021. [16]A. Togo, F. Oba, I. Tanaka, and K. Tatsumi, “First-principles calculations of native defects in tin monoxide,” Phys. Rev. B, vol. 74, no. 19, p. 195128, Nov. 2006. [17]Z. Ouyang et al., “Research Progress of p-Type Oxide Thin-Film Transistors,” Materials, vol. 15, no. 14, Jul. 2022. [18]A. Liu et al., “Selenium-alloyed tellurium oxide for amorphous p-channel transistors,” Nature, vol. 629, no. 8013, pp. 798–802, May 2024. [19]Z. Wang, P. K. Nayak, J. A. Caraveo-Frescas, and H. N. Alshareef, “Recent Developments in p-Type Oxide Semiconductor Materials and Devices,” Advanced Materials, vol. 28, no. 20, pp. 3831–3892, 2016 [20]J. Lu et al., “p-Type Oxide Thin-Film Transistor with Unprecedented Hole Field-Effect Mobility for an All-Oxide CMOS CFET-like Inverter Suitable for Monolithic 3D Integration,” Nano Lett., vol. 24, no. 48, pp. 15260–15267, Dec. 2024. [21]L. Y. Liang et al., “Phase and Optical Characterizations of Annealed SnO Thin Films and Their p-Type TFT Application,” J. Electrochem. Soc., vol. 157, no. 6, p. H598, Apr. 2010. [22]K. J. Saji, Y. P. Venkata Subbaiah, K. Tian, and A. Tiwari, “P-type SnO thin films and SnO/ZnO heterostructures for all-oxide electronic and optoelectronic device applications,” Thin Solid Films, vol. 605, pp. 193–201, Apr. 2016. [23]E. Fortunato et al., “Transparent p-type SnOx thin film transistors produced by reactive rf magnetron sputtering followed by low temperature annealing,” Appl. Phys. Lett., vol. 97, no. 5, p. 052105, Aug. 2010. [24]A. Togo, F. Oba, I. Tanaka, and K. Tatsumi, “First-principles calculations of native defects in tin monoxide,” Phys. Rev. B, vol. 74, no. 19, p. 195128, Nov. 2006. [25]S. Cahen, N. David, J. M. Fiorani, A. Maı̂tre, and M. Vilasi, “Thermodynamic modelling of the O–Sn system,” Thermochim. Acta, vol. 403, no. 2, pp. 275–285, Jul. 2003. [26]J. A. Caraveo-Frescas, P. K. Nayak, H. A. Al-Jawhari, D. B. Granato, U. Schwingenschlögl, and H. N. Alshareef, “Record Mobility in Transparent p-Type Tin Monoxide Films and Devices by Phase Engineering,” ACS Nano, vol. 7, no. 6, pp. 5160–5167, Jun. 2013. [27]G. Beensh-Marchwicka, L. Kròl-Stȩpniewska, and A. Misiuk, “Influence of annealing on the phase composition, transmission and resistivity of SnOx thin films,” Thin Solid Films, vol. 113, no. 3, pp. 215–224, Mar. 1984. [28]C.-W. Ou et al., “Anomalous p-channel amorphous oxide transistors based on tin oxide and their complementary circuits,” Appl. Phys. Lett., vol. 92, no. 12, Mar. 2008. [29]H. Yabuta et al., “Sputtering formation of p-type SnO thin-film transistors on glass toward oxide complimentary circuits,” Appl. Phys. Lett., vol. 97, no. 7, p. 072111, Aug. 2010. [30]I.-T. Cho, M. U, S.-H. Song, J.-H. Lee, and H.-I. Kwon, “Effects of air-annealing on the electrical properties of p-type tin monoxide thin-film transistors,” Semicond. Sci. Technol., vol. 29, no. 4, p. 045001, Feb. 2014. [31]K.-H. Bae, M. G. Shin, S.-H. Hwang, H.-S. Jeong, D.-H. Kim, and H.-I. Kwon, “Electrical Performance and Stability Improvement of p-Channel SnO Thin-Film Transistors Using Atomic-Layer-Deposited Al₂O₃ Capping Layer,” IEEE Access, vol. 8, pp. 222410–222416, 2020. [32]J. Han et al., “High-Mobility SnO Enabled by Doping-Induced Interstitial Oxygen for All-Oxide Complementary Logics,” Advanced Functional Materials, vol. 35, no. 27, p. 2500132, 2025. [33]Y. Zhang et al., “Ultralow P-Type Contact Resistance Enabled by Evaporated SnS Contacts,” Nano Lett., vol. 26, no. 9, pp. 3026–3033, Mar. 2026. [34]A. Bashir, T. I. Awan, A. Tehseen, M. B. Tahir, and M. Ijaz, “Interfaces and surfaces,” in Chemistry of Nanomaterials, Elsevier, 2020, pp. 51–87. [35]R. W. Johnson, A. Hultqvist, and S. F. Bent, “A brief review of atomic layer deposition: from fundamentals to applications,” Mater. Today, vol. 17, no. 5, pp. 236–246, Jun. 2014. [36]Anton Paar. X-ray diffraction (XRD). Retrieved July 31, 2026, from https://wiki.anton-paar.com/tw-zh/x-ray-diffraction-xrd/ [37] Measurlabs. Grazing incidence X-ray diffraction (GI-XRD). Retrieved July 31, 2026, from https://measurlabs.com/methods/grazing-incidence-x-ray-diffraction-gixrd/ [38] Chastain, Jill, and Roger C. King Jr." Handbook of X-ray photoelectron spectroscopy." Perkin-Elmer Corporation (1992) [39]Grimmgroup Research. XPS and UPS background. Retrieved July 31, 2026, from https://grimmgroup.net/research/xps/background/ [40]C. C. Wang et al., “P-type SnO Semiconductor Transistor and Application,” in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2024, pp. 1–2. [41]L. A. Rodríguez-Guadarrama, J. Escorcia-García, I. L. Alonso-Lemus, and J. Campos-Álvarez, “Synthesis of π-SnS thin films through chemical bath deposition: effects of pH, deposition time, and annealing temperature,” J. Mater. Sci. Mater. Electron., vol. 32, no. 6, pp. 7464–7480, Mar. 2021. [42]Y. Wang et al., “S-doped porous carbon confined SnS nanospheres with enhanced electrochemical performance for sodium-ion batteries,” J. Mater. Chem. A, vol. 6, no. 37, pp. 18286–18292, 2018. [43] W. Zhang et al., “Enhanced performance of p-type SnOx thin film transistors through defect compensation,” Journal of Physics: Condensed Matter, vol. 34, no. 40, p. 404003, 2022. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103699 | - |
| dc.description.abstract | 本論文主要開發具備低溫後段製程相容性的p型氧化亞錫（SnO）薄膜電晶體，目標是開發可應用於單體三維積體電路的p型氧化物元件，滿足低溫製程、低功耗操作與高密度整合的需求。SnO具有本質p型導電特性，且價帶頂由Sn 5s與 O 2p 軌域混成形成，具有較佳的電洞傳輸能力。但是SnO薄膜容易受到缺陷態與較高背景電洞濃度影響，導致元件漏電流偏高與穩定性受限。所以本研究導入CVD 硫化後處理技術，藉由硫元素對SnO通道進行摻雜，來降低缺陷相關漏電路徑並提升元件電性與可靠度。
本研究成功利用CVD系統對SnO TFT進行硫化後處理。實驗結果顯示，本研究所製作的留話條件可在230°C的低溫條件進行製程，本實驗硫化條件可使SnO TFT 的off current降低約兩個數量級，on/off current ratio提升約1–2個數量級，並改善次臨界擺幅，顯示硫化處理能有效抑制漏電流也可以提升閘極控制能力。此改善是因為硫元素導入後，與SnO薄膜中的缺陷或未飽和鍵結反應，減少缺陷輔助的漏電路徑。此外，也有透過XPS、XRD與TEM等材料分析方法確認硫化後薄膜之化學鍵結、晶體結構與截面形貌。 在可靠度分析方面，也透過正偏壓應力與負偏壓應力測試評估硫化處理對元件穩定性的影響。由結果顯示硫化後SnO TFT相較於pristine元件有較小的臨界電壓漂移，表示硫化處理可降低偏壓操作下的缺陷捕捉效應，去提升元件穩定性。也可以確定硫化後元件在長時間偏壓應力下，仍可維持較穩定的臨界電壓與關態電流表現，並比pristine元件有較佳的長時間操作穩定性與耐久度。 綜合以上結果，本研究成功開發出一套相容於低溫後段製程之p型SnO TFT 製程，並證明CVD硫化處理可有效改善SnO TFT的漏電流、開關特性、次臨界擺幅與偏壓穩定性。未來希望透過本製程具備低溫與後段整合相容的優勢，可進一步應用於低功耗 CMOS 元件及 Monolithic 3D IC 之垂直整合架構，作為發展 p 型氧化物半導體元件的可行方案。 | zh_TW |
| dc.description.abstract | This thesis focuses on the development of low-temperature BEOL-compatible p-type SnO thin-film transistors for monolithic 3D integrated circuits. SnO is a promising p-type oxide semiconductor due to its intrinsic p-type conductivity and favorable hole transport properties. However, defect states and high background hole concentration in SnO thin films lead to high leakage current and limited stability. Therefore, we used CVD sulfurization post-treatment to modify the SnO channel, reduce defect-related leakage paths, and improve device performance and reliability.
In this study, SnO TFTs were successfully sulfurized using CVD system at a low temperature of 230 °C. After sulfurization, the off current was reduced by approximately two orders, the on/off current ratio was improved by about 1–2 orders, and the subthreshold swing was enhanced. These improvements indicate that sulfurization effectively suppresses defect-related leakage paths and improves gate control. We also used XPS, XRD, and TEM analyses to confirm the chemical bonding, crystal structure, and cross-sectional morphology of the sulfurized SnO thin films. For reliability analysis, positive and negative bias stress tests were performed to evaluate device stability. The sulfurized SnO TFTs showed a smaller threshold voltage shift than the pristine devices, indicating that sulfurization can reduce defect trapping under bias stress. In addition, the sulfurized devices maintained more stable threshold voltage and off-current characteristics during long-term operation. These results confirm that sulfurization effectively improves the reliability and stability of SnO TFTs. Overall, this study successfully developed a low-temperature BEOL-compatible p-type SnO TFT process. The results show that CVD sulfurization can effectively reduce leakage current, improve switching characteristics and subthreshold swing, and enhance bias stability. Therefore, this process shows potential for low-power CMOS devices and vertically integrated Monolithic 3D IC applications, offering a feasible approach for the development of p-type oxide semiconductor devices. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-08-19T16:06:37Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-08-19T16:06:37Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii ABSTRACT iv 目次 v 圖次 viii 表次 xiii 第一章 緒論 1 1.1 半導體的發展歷程 1 1.2 單片型三維整合技術發展背景 2 1.3 金屬氧化物半導體薄膜電晶體發展 3 1.4 研究動機 5 第二章 理論與文獻回顧 8 2.1 薄膜電晶體簡介 8 2.1.1 薄膜電晶體之結構 8 2.1.2 薄膜電晶體之元件參數 9 2.2 p型金屬氧化物半導體簡介 13 2.2.1氧化亞錫的發展 13 2.2.2 氧化亞錫特性與結構 14 2.2.3 氧化亞錫的能階與缺陷 14 2.2.4 錫-氧（Sn-O）系統的相圖 17 2.3 p型氧化亞錫薄膜電晶體之發展歷程 19 第三章 實驗原理與方法 31 3.1 製程設備簡介 31 3.1.1 步進式曝光機（Stepper Aligner） 31 3.1.2電子束金屬蒸鍍機 （Electron Beam Evaporator） 32 3.1.3感應耦合電漿離子蝕刻機(Inductively coupled plasma-reaction ion Etching) 33 3.1.4 射頻磁控濺鍍系統 34 3.1.5原子層沉積系統 35 3.1.6化學氣相沉積（Chemical Vapor Deposition, CVD） 36 3.2 量測儀器簡介 38 3.2.1穿透式電子顯微鏡(Transmission Electron Microscope) 38 3.2.2拉曼光譜儀 38 3.2.3 X光繞射儀(X-ray Diffraction) 39 3.2.4 X射線光電子能譜(X-ray photoelectron spectroscopy) 41 3.2.5元件電性量測系統 42 3.3 氧化亞錫電晶體製備方式 44 3.3.1 電極微影製程 44 3.3.2金屬電極沉積與掀離(lift off) 45 3.3.3曝光微影與蝕刻(etching) 46 3.3.4 氧化亞錫薄膜電晶體電性量測方法 47 3.3.5 氧化亞錫薄膜硫化處理方法 48 第四章 結果與討論 50 4.1 氧化亞錫電晶體材料分析 50 4.1.1 拉曼確認氧化亞錫薄膜 50 4.1.2 XRD確認氧化亞錫薄膜晶相 51 4.1.3 XPS確認氧化亞錫薄膜材料狀況 53 4.2 氧化亞錫電晶體元件電性分析 54 4.2.1蝕刻製程優化 54 4.2.2不同蝕刻製程的電性表現 56 4.3 硫化氧化亞錫電晶體元件分析 58 4.3.1 CVD 硫化參數設定及儀器設備 58 4.3.2 硫化氧化亞錫電晶體電性表現 60 4.4 硫化處理後氧化亞錫薄膜之材料分析 66 4.4.1氧化亞錫薄膜硫化前後之XPS分析 66 4.4.2 氧化亞錫薄膜硫化前後之XRD、Raman分析 71 4.4.3 氧化亞錫薄膜硫化前後TEM分析 73 4.5 硫化處理後氧化亞錫可靠度分析 74 4.6 本實驗與氧化亞錫過去文獻比較 77 4.7 鈍化層對電性的影響 78 第五章 結論與未來展望 81 5.1 結論 81 5.2 未來展望 83 參考文獻 84 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 氧化亞錫 | - |
| dc.subject | p型薄膜電晶體 | - |
| dc.subject | 硫化處理 | - |
| dc.subject | 後段製程 | - |
| dc.subject | 單體三維積體電路 | - |
| dc.subject | 鈍化層 | - |
| dc.subject | Tin monoxide | - |
| dc.subject | P-type thin-film transistor | - |
| dc.subject | Sulfurization | - |
| dc.subject | Back-end-of-line process | - |
| dc.subject | Monolithic three-dimensional integrated circuit | - |
| dc.subject | Passivation layer | - |
| dc.title | 相容於低溫後段製程之P型SnO薄膜電晶體硫化技術開發與特性研究 | zh_TW |
| dc.title | Development and Characterization of Sulfurization Process for Low-Temperature BEOL-Compatible p-Type SnO Thin-Film Transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳奕君;吳肇欣;陳美杏 | zh_TW |
| dc.contributor.oralexamcommittee | I-Chun Cheng;Chao-Hsin Wu;Mei-Hsin Chen | en |
| dc.subject.keyword | 氧化亞錫; p型薄膜電晶體; 硫化處理; 後段製程; 單體三維積體電路; 鈍化層 | zh_TW |
| dc.subject.keyword | Tin monoxide; P-type thin-film transistor; Sulfurization; Back-end-of-line process; Monolithic three-dimensional integrated circuit; Passivation layer | en |
| dc.relation.page | 87 | - |
| dc.identifier.doi | 10.6342/NTU202603001 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2026-08-06 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 元件材料與異質整合學位學程 | - |
| dc.date.embargo-lift | 2029-07-31 | - |
| 顯示於系所單位： | 元件材料與異質整合學位學程 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-114-2.pdf 此日期後於網路公開 2029-07-31 | 5.47 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。