應用於超導量子讀取系統之低溫CMOS低功耗寬頻低雜訊放大器設計與實現

Abstract

隨著超導量子計算技術的快速發展，量子位元數量的規模化對讀取介面電路提出了嚴峻挑戰。為了克服傳統室溫電子設備需透過大量長電纜連接至低溫腔體所帶來的訊號損耗與熱負載問題，將射頻前端電路整合至 4 K 低溫環境的 CryoCMOS 技術已成為關鍵解決方案。本論文旨在設計並實作適用於4 K環境、頻寬涵蓋4–10 GHz之寬頻低雜訊放大器，以滿足頻分多工量子讀取系統之需求。 本研究採用TSMC 28 nm CMOS製程，設計並實作了源極電感退化與交叉電容耦合共閘極（CCC-CG）兩款不同架構之低雜訊放大器。源極退化架構利用電感性回授達成低雜訊與良好輸入匹配，而CCC-CG架構則透過交叉耦合電容提升等效轉導(𝑔𝑚)，在低功耗下實現寬頻匹配與增益平坦度。電路設計過程中考量了低溫下 MOS 電晶體載子遷移率提升與閾值電壓漂移之特性，並針對 Chip-on-Board (COB)封裝引入的打線寄生效應進行了嚴謹的電磁模擬與優化。量測結果顯示，兩款晶片在常溫環境下皆功能正常，且透過引入打線電感與PCB寄生模型之擬合模擬，成功驗證了實測頻率偏移之物理成因。在4 K低溫量測中，受惠於金屬導線電阻下降與電晶體轉導提升，電路展現出優異的增益與雜訊性能。本研究成功驗證了 28 nm CMOS 製程應用於高效能量子讀取介面之可行性，並建立了從元件建模、電路設計到低溫封裝量測的完整開發流程，為未來大規模量子電腦之控制晶片設計提供重要參考。

With the rapid development of superconducting quantum computing technology, the scaling of qubit numbers poses severe challenges to readout interface circuits. To overcome the signal attenuation and thermal load issues caused by connecting traditional room-temperature electronics to the cryogenic chamber via massive long cables, integrating RF front-end circuits into the 4 K cryogenic environment using Cryo-CMOS technology has become a key solution. This thesis aims to design and implement broadband low-noise amplifiers (LNAs) suitable for the 4 K environment, covering a bandwidth of 4 – 10 GHz, to meet the requirements of frequency-division multiplexing (FDM) quantum readout systems. This study utilizes the TSMC 28 nm CMOS process to design and implement two different LNA architectures: Source Inductive Degeneration and Cross-Coupled Capacitor Common-Gate (CCC-CG). The source degeneration architecture utilizes inductive feedback to achieve low noise and good input matching, while the CCC-CG architecture enhances effective transconductance through cross-coupled capacitors, achieving broadband matching and gain flatness with low power consumption. The circuit design process considered the characteristics of carrier mobility enhancement and threshold voltage shift of MOS transistors at cryogenic temperatures. Furthermore, rigorous electromagnetic simulation and optimization were conducted to address the wire-bonding parasitic effects introduced by Chip-on-Board (COB) packaging. Measurement results show that both chips function normally at room temperature. Through fitting simulations incorporating wire bond inductance and PCB parasitic models, the physical causes of the measured frequency shift were successfully verified. In 4 K cryogenic measurements, benefiting from the reduced resistance of metal interconnects and the increased transistor transconductance, the circuits demonstrated excellent gain and noise performance. This research successfully verifies the feasibility of applying the 28 nm CMOS process to high-performance quantum readout interfaces and establishes a complete development flow—from device modeling and circuit design to cryogenic packaging measurement—providing an important reference for the design of control chips for future large-scale quantum computers.