一個使用自適應斜率電荷分享數位時間轉換器之分數式頻率數位二位元相位偵測鎖相迴路設計

Abstract

本論文提出一個分數式頻率鎖相迴路架構，主要子電路包括二位元相位偵測器(Bang-Bang Phase Detector, BBPD)、數位濾波器(Digital Loop Filter, DLF)、壓控震盪器(Voltage-Controlled Oscillator, VCO)、多模數除頻器(Multi-Modulus Divider, MMD)、ΔΣ調變器(Delta-Sigma Modulator, DSM)以及數位時間轉換器(Digital-to-Time Converter, DTC)。為了產生分數式頻率，本篇採用DSM來控制MMD的除數。由於實際設計上數位電路的位元數有限，DSM本身會有一定的量化雜訊，在轉換之下鎖相迴路的輸出產生相對應的分數突波。其中一個消除量化雜訊的方式為在參考路徑或迴授路徑上加上DTC產生相對應的延遲輸出，進而補償量化雜訊帶來的相位誤差。 實際在DTC設計上會帶有一定的積分非線性度(Integral Non-Linearity, INL)，使得無法完整消除量化雜訊，故本篇基於INL考量下以固定斜率數位時間轉換器(Constant-Slope DTC, CSDTC)作為設計DTC的基礎架構，並提出一個符號偵測演算法(Sign-Detected Algorithm, SDA)，利用BBPD的輸出在不同INL下的輸出模式差異和DSM的量化雜訊做比對，為了能夠在背景校正DTC的INL，進而改善鎖相迴路的整體輸出表現。 本電路採用40奈米CMOS製程設計，其核心面積為0.264 mm2，整體功耗為4.15mW，操作頻率在5.5 GHz。DTC的INL表現在Pre-Sim及Post-Sim模擬上分別為 0.07 LSB和 0.15 LSB，此外本電路輸出參考突波(Reference Spur)以及分數突波(Fractional Spur)表現分別為 -54 dBc 與 -50 dBc。

This paper proposes a Fractional-N phase-locked loop (FNPLL) architecture. The main sub-circuits include Bang-Bang Phase Detector (BBPD), Digital Loop Filter (DLF), Voltage-Controlled Oscillator (VCO), Multi-Modulus Divider (MMD), Delta-Sigma Modulator (DSM), and Digital-to-Time Converter (DTC). To generate fractional frequencies, DSM is used to control the division ratio of the MMD. Due to the limited bit resolution in practical digital circuit designs, the DSM inherently introduces quantization noise, which results in corresponding fractional spurs at the PLL output. One method to mitigate quantization noise is to add a DTC in the reference path or feedback path to generate a corresponding output delay, thereby compensating for the phase error caused by quantization noise. However, the DTC design typically exhibits a certain level of Integral Non-Linearity (INL), which prevents complete elimination of the quantization noise. To address this, Constant-Slope Digital-to-Time Converter (CSDTC) is adopted as the base architecture for the DTC, considering the INL effects. This work also proposes Sign-Detected Algorithm (SDA), which compares the output patterns of the BBPD under various INL conditions with the quantization noise of the DSM. The goal is to enable background calibration of the DTC's INL, thereby improving the overall performance of the PLL output. The proposed circuit is implemented in a 40-nm CMOS process with core area of 0.264 mm² and total power consumption of 4.15 mW, operating at 5.5 GHz. According to pre-layout simulation and post-layout simulation, the INL performance of the DTC is 0.07 LSB to 0.15 LSB, respectively. The reference spur and fractional spur of the circuit are -54 dBc and -50 dBc, respectively.