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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 張澔文 | zh_TW |
| dc.contributor.author | Hao-Wen Chang | en |
| dc.date.accessioned | 2026-02-11T16:46:50Z | - |
| dc.date.available | 2026-02-12 | - |
| dc.date.copyright | 2026-02-11 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-02-04 | - |
| dc.identifier.citation | [1] C.-C. Hung et al., “A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique,” in IEEE International of Solid-State Circuits Conference (ISSCC), pp. 328–330, Feb. 2025.
[2] W. Wu et al., “A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 56, no. 12, pp. 3756–3767, Dec. 2021. [3] Y. Zhang et al., “A Fractional-N PLL With Space–Time Averaging for Quantization Noise Reduction,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 3, pp. 602–614, Mar. 2020. [4] D. Murphy et al., “A Calibration-Free Fractional-N Analog PLL with Negligible DSM Quantization Noise,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 9, pp. 2513–2525, Sep. 2023. [5] C. Venerus, and I. Galton, “Quantization Noise Cancellation for FDC-Based Fractional-N PLLs,” in IEEE Transactions on Circuits and Systems II, Express Briefs (TCAS-II), vol. 62, no. 12, pp. 1119–1123, Dec. 2015. [6] D. Tasca et al., “A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 12, pp. 2745–2758, Dec. 2011. [7] W. C. Lindsey et al., "A survey of digital phase-locked loops," in Proceedings of the IEEE, vol. 69, no. 4, pp. 410–431, Apr. 1981. [8] A. S Kamath and B. Chattopadhyay, “A Wide Output Range, Mismatch Tolerant Sigma Delta DAC for Digital PLL in 90nm CMOS,” in IEEE International Symposium on Circuits and Systems (ISCAS), May. 2012 [9] P. Dudek and S. Szczepan´ski, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 35, no. 2, pp. 240–247, Feb. 2000. [10] J. Tangudu et al., "Quantization noise improvement of time to digital converter (TDC) for ADPLL," in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1020–1023, May. 2009. [11] P. Madoglio, " Quantization effects in all-digital phase-locked loops," in IEEE Transactions on Circuits and Systems II, Express Briefs (TCAS-II), vol. 43, no. 12, pp. 2776–2786, Dec. 2008. [12] N. D. Dalt, “Linearized analysis of a digital bang–bang PLL and its validity limits applied to jitter transfer and jitter generation,” in IEEE Transactions on Circuits and Systems I, Regular Papers (TCAS-I), vol. 55, no. 11, pp. 3663–3675, Dec. 2008. [13] H. Xu and A. A. Abidi, “Design methodology for phase-locked loops using binary (bang–bang) phase detectors,” in IEEE Transactions on Circuits and Systems I, Regular Papers (TCAS-I), vol. 64, no. 7, pp. 1637–1650, Jul. 2017. [14] S. M. Dartizio, et al., “A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 6, pp. 1723–1735, Jun. 2022. [15] L. Bertulessi, et al., “A 30-GHz Digital Sub-Sampling Fractional-N PLL with −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 12, pp. 3493-3502, Dec. 2019. [16] S. M. Dartizio, et al., “A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 12, pp. 3320–3337, Dec. 2023. [17] M. P. Kennedy, et al., “A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs,” in IEEE International of Solid-State Circuits Conference (ISSCC), pp. 194–196, Feb. 2024. [18] Q. J. Gu and Z. Gao, “A CMOS High Speed Multi-Modulus Divider with Retiming for Jitter Suppression,” in IEEE Microwave and Wireless Components Letters (MWCL), vol. 23, no. 10, Oct. 2013. [19] L. W. Couch, “Digital and Analog Communication Systems”, Fourth Edition, New York: Macmillan Co., 1993. [20] B. Razavi, “RF Microelectronics,” Second Edition, New York: Hamilton, 2011. [21] F. Song, Y. Zhao, B. Wu, L. Tang, L. Lin, and B. Razavi, “A fractional-N synthesizer with 110 fsrms jitter and a reference quadrupler for wideband 802.11ax,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2019, pp. 264–266. [22] Y.-C. Yang and S.-S. Lu, “A quantization noise pushing technique for 16 fractional-N frequency synthesizers,” in IEEE Transaction on Microwave Theory and Techniques (T-MTT), vol. 56, no. 4, pp. 817–825, Apr. 2008. [23] M. Gupta and B.-S. Song, “A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2842–2851, Dec. 2006. [24] A. Swaminathan, K. J. Wang, and I. Galton, “A wide-bandwidth 2.4 GHz ISM-band fractional-N PLL with adaptive phase-noise cancellation,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 12, pp. 2639–2650, Dec. 2007. [25] V. K. Chillara et al., “An 860 μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth smart and ZigBee) applications,” in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 172–173. [26] Bangan Liu, et al., “A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration,” in IEEE Transactions on Circuits and Systems I, Regular Papers (TCAS-I), vol. 64, no. 7, pp. 603–616, Feb. 2024. [27] N. Markulic, K. Raczkowski, P. Wambacq, and J. Craninckx, “A 10-bit, 550-fs step digital-to-time converter in 28 nm CMOS,” in 40th European Solid-State Circuits Conference (ESSCIRC), pp. 79–82, Sep. 2014. [28] M. Rossoni, et al., “A Low-Jitter Fractional-N Digital PLL Adopting a Reverse Concavity Variable-Slope DTC,” in IEEE International of Solid-State Circuits Conference (ISSCC), pp. 188-191, Feb. 2024. [29] J. Z. Ru, et al., “A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 50, no. 6, pp. 1412–1423, Jun. 2015. [30] J. M. Daga and D. Auvergne, et al., “A Comprehensive Delay Macro Modeling for Sub-micrometer CMOS Logics,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 34, no. 1, pp. 42–55, Jan. 1999. [31] T. M. Vo, “Analysis of LMS Gain Variation in DTC-Based Fractional-N Digital PLLs,” in IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2019. [32] P. Chen, X. Huang, and R. B. Staszewski, “Fractional Spur Suppression in All-Digital Phase-Locked Loops,” in Proc. IEEE International. Symposium Circuits Syst. (ISCAS), pp. 2565–2568, May 2015. [33] S. Levantino, G. Marzin, and C. Samori, “An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 49, no. 8, pp. 1762–1772, Aug. 1999. [34] C.-R. Ho and M. S.-W. Chen, “A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <−73dBc Fractional Spur and <−110dBc Reference Spur in 65nm CMOS,” in IEEE International of Solid-State Circuits Conference (ISSCC), pp. 190-192, Feb. 2016. [35] D. Xu, et al., “A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter,” in IEEE International of Solid-State Circuits Conference (ISSCC), pp. 192-194, Feb. 2024. [36] Y. Liu, et al., “A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques,” in IEEE Transactions on Circuits and Systems I, Regular Papers (TCAS-I), vol. 71, no. 2, pp. 526–536, Feb. 2024. [37] A. Santiccioli, et al., “Power-jitter trade-off analysis in digital-to-time converters,” in Electronics Letters, vol. 53, no. 5, pp. 306–308, Mar. 2017. [38] Tuan M. Vo, “Analysis of LMS Gain Variation in DTC-Based Fractional-N Digital PLLs,” in IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Nov. 2019. [39] X. Wang, “Comparison of DTC Segmentation Methods in Fractional-N Frequency Synthesizers,” in IEEE International Symposium on Circuits and Systems (ISCAS), May 2024. [40] S. Haykin, “Adaptive Filter Theory” Fifth Edition, Pearson Education, 2014. [41] S. Jang, et al., “A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm,” in Journal of Solid-State Circuits (JSSC), vol. 59, no. 12, pp. 3884–3897, Dec. 2024. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101613 | - |
| dc.description.abstract | 本論文提出一個分數式頻率鎖相迴路架構，主要子電路包括二位元相位偵測器(Bang-Bang Phase Detector, BBPD)、數位濾波器(Digital Loop Filter, DLF)、壓控震盪器(Voltage-Controlled Oscillator, VCO)、多模數除頻器(Multi-Modulus Divider, MMD)、ΔΣ調變器(Delta-Sigma Modulator, DSM)以及數位時間轉換器(Digital-to-Time Converter, DTC)。為了產生分數式頻率，本篇採用DSM來控制MMD的除數。由於實際設計上數位電路的位元數有限，DSM本身會有一定的量化雜訊，在轉換之下鎖相迴路的輸出產生相對應的分數突波。其中一個消除量化雜訊的方式為在參考路徑或迴授路徑上加上DTC產生相對應的延遲輸出，進而補償量化雜訊帶來的相位誤差。
實際在DTC設計上會帶有一定的積分非線性度(Integral Non-Linearity, INL)，使得無法完整消除量化雜訊，故本篇基於INL考量下以固定斜率數位時間轉換器(Constant-Slope DTC, CSDTC)作為設計DTC的基礎架構，並提出一個符號偵測演算法(Sign-Detected Algorithm, SDA)，利用BBPD的輸出在不同INL下的輸出模式差異和DSM的量化雜訊做比對，為了能夠在背景校正DTC的INL，進而改善鎖相迴路的整體輸出表現。 本電路採用40奈米CMOS製程設計，其核心面積為0.264 mm2，整體功耗為4.15mW，操作頻率在5.5 GHz。DTC的INL表現在Pre-Sim及Post-Sim模擬上分別為 0.07 LSB和 0.15 LSB，此外本電路輸出參考突波(Reference Spur)以及分數突波(Fractional Spur)表現分別為 -54 dBc 與 -50 dBc。 | zh_TW |
| dc.description.abstract | This paper proposes a Fractional-N phase-locked loop (FNPLL) architecture. The main sub-circuits include Bang-Bang Phase Detector (BBPD), Digital Loop Filter (DLF), Voltage-Controlled Oscillator (VCO), Multi-Modulus Divider (MMD), Delta-Sigma Modulator (DSM), and Digital-to-Time Converter (DTC). To generate fractional frequencies, DSM is used to control the division ratio of the MMD. Due to the limited bit resolution in practical digital circuit designs, the DSM inherently introduces quantization noise, which results in corresponding fractional spurs at the PLL output.
One method to mitigate quantization noise is to add a DTC in the reference path or feedback path to generate a corresponding output delay, thereby compensating for the phase error caused by quantization noise. However, the DTC design typically exhibits a certain level of Integral Non-Linearity (INL), which prevents complete elimination of the quantization noise. To address this, Constant-Slope Digital-to-Time Converter (CSDTC) is adopted as the base architecture for the DTC, considering the INL effects. This work also proposes Sign-Detected Algorithm (SDA), which compares the output patterns of the BBPD under various INL conditions with the quantization noise of the DSM. The goal is to enable background calibration of the DTC's INL, thereby improving the overall performance of the PLL output. The proposed circuit is implemented in a 40-nm CMOS process with core area of 0.264 mm² and total power consumption of 4.15 mW, operating at 5.5 GHz. According to pre-layout simulation and post-layout simulation, the INL performance of the DTC is 0.07 LSB to 0.15 LSB, respectively. The reference spur and fractional spur of the circuit are -54 dBc and -50 dBc, respectively. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-02-11T16:46:50Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-02-11T16:46:50Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員會審定 i
致謝 ii 摘要 iii Abstract iv Table of Contents vi List of Figures ix List of Table xiii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Thesis Overview 2 Chapter 2 Fundamental of Fractional-N Bang-Bang Digital PLL 4 2.1 Digital Phase-Locked Loops 4 2.2 Phase Detector for Digital Phase-Locked Loops 6 2.2.1 Time-to-Digital Converter (TDC) 6 2.2.2 Bang-Bang Phase Detector (BBPD) 7 2.3 Fundamentals of Delta-Sigma Modulator (DSM, ΔΣ) 9 2.3.1 Single-Stage DSM 10 2.3.2 Multi-Stage Noise Shaping DSM (MASH DSM) 10 2.3.3 DSM Noise in Fractional-N Bang-Bang PLLs 11 2.4 DSM Quantization Noise Suppression 13 2.4.1 Raised DSM Operating Frequency 13 2.4.2 DAC cancellation 14 2.4.3 Digital-to-Time Converter (DTC) cancellation 15 Chapter 3 Introduction of DTC and Linearity Improvement Technology 16 3.1 Overview of the DTC Architecture 17 3.1.1 Path Selection DTC 17 3.1.2 Variable-Slope DTC 18 3.1.3 Constant-Slope DTC 20 3.1.4 Comparison of DTC Structure 22 3.2 Analysis on DTC Non-Ideality 22 3.2.1 Gain Error (ΔS) 23 3.2.2 Integral Non-Linearity (INL) 24 3.2.3 Impact of DTC INL on Spur Performance in FNPLLs 25 3.3 Prior Arts of DTC Linearization in FNPLL 27 3.3.1 Digital Pre-Distortion (DPD) 27 3.3.2 Multi-Tone Spur Cancellation Loop 28 3.3.3 Pseudo-Differential DTC 29 3.3.4 Inverse Constant-Slope DTC (ICS-DTC) 31 3.3.5 Summary 33 3.4 Proposed Slope-Adaptable Charging-Sharing DTC (SA-CSHDTC) 33 3.4.1 Prototype of Charging-Sharing DTC (CSHDTC) 33 3.4.2 INL sources in CSHDTC 35 3.4.3 Charging Slope Linearization – INL compensated varactor 38 3.4.4 Proposed Slope-Adaptation Mechanism 41 3.4.5 Overall Structure 46 Chapter 4 Design of a 5.5 GHz DTC-based Fractional-N Bang-Bang PLL 48 4.1 Proposed DTC-based FN-BBPLL with Sign Detected Algorithm 48 4.1.1 Architecture 48 4.1.2 Specification and System Coefficient 49 4.2 Analog Circuit 54 4.2.1 Bang-Bang Phase Detector (BBPD) 54 4.2.2 LC-based Voltage-Controlled Oscillator (LC-VCO) 55 4.2.3 Multi-Modulus Divider (MMD) 57 4.2.4 Coarse DTC --- Slope-Adaptable Charge-Sharing DTC (SA-CSHDTC) 59 4.2.5 Fine DTC --- Variable-Slope DTC (VSDTC) 69 4.3 Digital Circuit 72 4.3.1 Digital Loop Filter (DLF) 72 4.3.2 ΔΣ + DAC 73 4.3.3 MASH 1-1 DSM 74 4.3.4 Least-Mean Square Algorithm (LMS) 75 4.3.5 Sign-Detected Algorithm (SDA) 81 4.4 Overall PLL Simulation 84 Chapter 5 Measurement Results 85 5.1 Die Photograph 85 5.2 Measurement Setup 86 5.3 Measurement Results and Issues in Measurement 86 Chapter 6 Conclusion and Future Works 89 6.1 Conclusion 89 6.2 Future Works 90 6.2.1 DTC Range Reduction 90 6.2.2 LMS Loop Acceleration 91 6.2.3 Proposed DTC-based FNPLL with Renovated Structure 91 References 92 | - |
| dc.language.iso | en | - |
| dc.subject | 分數式頻率鎖相迴路 | - |
| dc.subject | 二位元相位偵測器 | - |
| dc.subject | ΔΣ調變器 | - |
| dc.subject | 量化雜訊 | - |
| dc.subject | 數位時間轉換器 | - |
| dc.subject | 積分非線性度 | - |
| dc.subject | 背景校正 | - |
| dc.subject | Fractional-N PLL | - |
| dc.subject | Bang-Bang Phase Detector (BBPD) | - |
| dc.subject | Delta-Sigma Modulator (DSM) | - |
| dc.subject | Quantization Noise | - |
| dc.subject | Digital-to-Time Converter (DTC) | - |
| dc.subject | Integral Non-Linearity (INL) | - |
| dc.subject | Background Calibration | - |
| dc.title | 一個使用自適應斜率電荷分享數位時間轉換器之分數式頻率數位二位元相位偵測鎖相迴路設計 | zh_TW |
| dc.title | Design of a Fractional-N Digital Bang-Bang PLL with Slope-Adaptable Charge-Sharing DTC | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李泰成;薛育理 | zh_TW |
| dc.contributor.oralexamcommittee | Tai-Cheng Lee;Yu-Li Hsueh | en |
| dc.subject.keyword | 分數式頻率鎖相迴路,二位元相位偵測器ΔΣ調變器量化雜訊數位時間轉換器積分非線性度背景校正 | zh_TW |
| dc.subject.keyword | Fractional-N PLL,Bang-Bang Phase Detector (BBPD)Delta-Sigma Modulator (DSM)Quantization NoiseDigital-to-Time Converter (DTC)Integral Non-Linearity (INL)Background Calibration | en |
| dc.relation.page | 97 | - |
| dc.identifier.doi | 10.6342/NTU202600594 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2026-02-06 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2031-02-02 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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