基於FPGA的PCIe低成本大量影像資料傳輸系統

Abstract

本論文研究目的為應用於製程產業曝光系統上，在電腦與微鏡裝置之間傳輸大量的曝光影像資料，為了加快影像資料傳輸的速度且確保資料皆正確無誤，本研究使用擁有高吞吐量、低延遲與資料錯誤重傳機制的PCIe傳輸協定，在FPGA上使用RIFFA(A Reusable Integration Framework for FPGA Accelerators)架構運行在PCIe(Peripheral Component Interconnect Express)上。RIFFA提供一個簡單的數據傳輸軟體API和一個AXI-Stream FIFO硬體界面，並處理PCIe協定的數據封包編碼與解碼，讓使用者能夠專注於實現應用邏輯而不是基本的PCIe連接界面，本研究改進RIFFA架構的封包處理以提升至Gen 3 ×8，使其吞吐量達到6603.17 MB/s。 本論文分為兩大研究主題討論，第一部分主題為基於RIFFA架構實現PCIe Gen 3 ×8的介面傳輸，電腦端以Linux Ubuntu作業系統的環境下，使用者透過簡單的API(A high-level Application Programming Interface)將資料利用PCIe協定傳送至VC709 FPGA(Field Programmable Gate Array)，在透過RIFFA的內部邏輯解碼、重排封包等，FPGA將資料解碼並進行資料處理後，再經由Aurora協議透過雙端QSFP+ (40G or 56G) FMC(Field-Programmable Mezzanine Card)模組接口傳送至DMD (Digital Micromirror Device)顯示。 第二部分主題，即為此VC709至Kintex-7的端對端橋接系統設計。在VC709 傳輸節點上，本研究設計了Chnl_dmd模組，其核心在於使用FIFO_O與FIFO_I 兩個非同步 FIFO，成功解決RIFFA核心與Aurora IP之間的時脈域轉換問題。在 Kintex-7接收節點上，則實作了Aurora2Mcu_blk 模組，其內含一個解多工器，將 Aurora傳來的256-bit高速資料流，轉換為64-bit資料流，以供後端MCU_blk與Dmd_ctl模組進行即時的影像矩陣運算與解碼。 實驗結果證實，此一完整的端對端系統能成功傳輸132,249,600 words的影像並正確成像。在總體傳輸時間上，本系統僅需0.42秒即完成傳輸。相較於現有的 10G Ethernet TCP-like方案所需的3.95秒，效能提升接近一個數量級，充分滿足了即時大量影像傳輸的嚴苛需求。

This thesis aims to develop a high-throughput, high-integrity data transmission system for industrial lithography applications, specifically for transferring large-scale exposure images between a host computer and a microlithography device. To achieve the required speed and data integrity, this research utilizes the Peripheral Component Interconnect Express (PCIe) protocol, renowned for its high throughput, low latency, and error-retry mechanisms. The system is implemented on an FPGA using the A Reusable Integration Framework for FPGA Accelerators (RIFFA) framework. RIFFA provides a simple software API and a streaming FIFO hardware interface, abstracting the complexities of the PCIe protocol and allowing the user to focus on application logic. A primary contribution of this research is the modification of the RIFFA framework's packet processing logic to support a PCIe Gen 3 ×8 interface, achieving a measured throughput of 6603.17 MB/s. This thesis discusses two main research topics. The first part details the implementation of the RIFFA-based PCIe Gen 3 ×8 interface. Operating on a Linux Ubuntu host, a user application utilizes the high-level API to transmit data via the PCIe protocol to a VC709 FPGA. On the FPGA, RIFFA's internal logic decodes and reorders the packets. After data processing, the data is transmitted to the Digital Micromirror Device (DMD) via the Aurora protocol using a dual QSFP+ (40G/56G) FMC module. The second part details the design of the end-to-end bridge system from the VC709 to a Kintex-7 FPGA. On the VC709 transmission node, this study designed the Chnl_dmd module, which utilizes two asynchronous FIFOs to successfully resolve the clock domain crossing (CDC) issue between the RIFFA core and the Aurora IP. On the Kintex-7 receiving node, an Aurora2Mcu_blk module was implemented. This module integrates a demultiplexer that converts the 256-bit high-speed Aurora data stream into a 64-bit data stream, feeding the backend MCU_blk and Dmd_ctl modules for real-time image matrix operations and decoding. Experimental results validate this complete end-to-end system, which successfully transmitted a 132,249,600-word image and displayed it correctly. The total transmission time was only 0.42 seconds, compared to the 3.95 seconds required by the existing 10G Ethernet TCP-like solution. This achievement represents a nearly order-of-magnitude performance increase, fully satisfying the stringent demands of real-time, high-throughput image transmission.