三相四線併網換流器電流測量誤差影響之分析與消除

Abstract

併網型換流器主要控制對象為輸出電流，因此電流的控制效果為衡量其品質的重要依據，而電流控制效果通常與所使用的電流感測器及周邊處理電路高度相關，然而完美無誤差的量測一般是不可能達到的，並且在三相四線換流器架構的操作下，電流量測誤差(CME)將會導致串聯分離電容盤的電壓產生偏移。除了需要定期進行校正外，還需要額外的分離電容盤電壓控制及其所需的元件，這些元件增加的成本、重量、以及額外控制皆會使此換流器架構的經濟效益受到影響。 本論文旨在abc參考坐標下，對多種線性電流控制方式之電流量測誤差問題進行全面的數學分析。為抑制電流量測誤差，本論文提出一種偏移抑制(OS)的通用解決方法，此偏移抑制方法可與不同的線性控制進行結合，將串聯分離電容電壓穩定在直流電壓中點附近。本論文更進一步提出分相「比例-諧振偏移抑制」(PROS)電流控制方法，除了在無需新增額外感測電路及電壓控制迴路下，能維持良好的交流輸出電流控制，更同時能將兩串連分離電容電壓皆收斂至直流電壓中點。本論文之分析及提出之方法均由電腦模擬進行驗證，並以3.75kW的實驗室原型機進行實作驗證。實驗結果顯示，在所提出的「比例-諧振偏移抑制」方法下，無論電流量測誤差為正負值皆能完全消除中性線直流電流誤差以及串連分離電容電壓偏移。除此之外，本論文所提出的「比例-諧振偏移抑制」同時展現了快速的響應特性，在具有電流量測誤差的情境下進行平衡與不平衡之間的三相功率切換，其直流電壓偏差衰減及三相電流進入穩態時間約為200ms及2.5ms。此一結果證實了本論文所提出的「比例-諧振偏移抑制」方法之有效性及其強健性。

Grid-connected inverters heavily depend on the grade of current detection and processing devices since their performance are assessed by the quality of the controlled currents. However, achieving perfect accuracy is not feasible. Moreover, in the case of three-phase four-wire inverters with split dc-link capacitors, current measurement error (CME) can result in the deviation of the split capacitor voltages. Despite periodic calibration, the economic advantage of the inverter topology is compromised due to the requirement of the split capacitor voltage control unit, which imposes more cost, weight, and control efforts. The objective of this dissertation is to develop comprehensive mathematical analysis to reveal the CME issues in the operation of various linear current control methods, constructed in the abc reference frame. A generalized solution based on the Offset Suppression (OS) function is proposed to mitigate the CME effects. The OS function can be combined with different linear controllers to inherently stabilize the capacitor voltages around the dc link midpoint value. Further advanced proposal is obtained through the architecture of the proposed per-phase Proportional Resonant Offset Suppression (PROS) current controller which can simultaneously achieve not only satisfactory ac performance but it can maintain both split capacitor voltages at their midpoint value, without extra sensors and controls. The theoretical analysis and the proposed solutions developed in this dissertation are verified by computer simulations and are validated through 3.75 kW laboratory prototype experiments. The experiments have shown that in the proposed PROS controller operation, zero dc neutral current error and zero dc split capacitor voltage deviation are achieved irrespective of the CME polarity. Moreover, the proposed PROS controller demonstrates fast transient responses: the decay time of the dc voltage deviation and the settling time of the three-phase grid currents are within approximately 200 ms and 2.5 ms, respectively, even in the presence of CME and during step transitions between balanced and unbalanced three-phase power exchanges. These findings validate the effectiveness of the proposed PROS controller and confirm the robustness of the controller design methodology developed in this dissertation.