一個使用具隱含共模共振與尾端回授振盪器之增益強化參考取樣式鎖相迴路

Abstract

本碩士論文提出一款第二型參考取樣式鎖相迴路（phase-locked loop），整合參考雙取樣相位偵測器（reference-double-sampling phase detector）、主動式增益提升電路（active gain-boosting cell），以及採用隱含共模共振（implicit common-mode resonance）技術的尾端回授電壓控制振盪器（tail-feedback voltage controlled oscillator），可同時降低鎖相迴路的帶內與帶外相位雜訊。其中參考雙取樣相位偵測器同時利用參考時脈之上升與下降沿，配合主動式增益提升電路放大採樣誤差電壓，有效提升相位偵測器增益並抑制電壓電流轉換單元 (G_m-cell) 所致之相位雜訊；隱含共模共振技術則進一步改善尾端回授電壓控制振盪器的內在雜訊表現。 晶片採 28 奈米CMOS 製程製造，其有效面積大約為 0.167 mm²；在電源電壓 1 V 供應下並運作於 6.4 GHz 時，功耗 14.83 mW。量測結果顯示，於 10 kHz 至 100 MHz 積分範圍內，此鎖相迴路的均方根抖動僅 77.3 fs，對應的效能指數（FoM）為 −250.5 dB，驗證了所提架構之優異效能。

This thesis introduces a type-II phase-locked loop (PLL) that incorporates a reference-double-sampling phase detector (RDSPD), a novel active gain-boosting cell (active GBC) and a tail-feedback voltage-controlled oscillator (TFVCO) with the implicit common mode resonance (ICMR) technique to minimized both in-band and out-band phase noise of the PLL simultaneously. The RDSPD utilized both rising and falling tranisistions of the reference clock, and the proposed active GBC amplify the sampled voltage error. Consequently, the phase detector gain is boosted effectively, and the phase noise from the "G" _"M" -cell is suppressed. In addition, by applying the ICMR technique on the TFVCO, the proposed VCO achieve low phase noise. Fabricated in a 28 nm CMOS technology, the implemented RDSPLL occupies an active area of 0.167 mm². Operating at 6.4 GHz from a 1 V supply, it consumes 14.83 mW. Experimental results demonstrate that the PLL achieves the root-mean-square (RMS) jitter of 77.3 fs over an integration range from 10 kHz to 100 MHz, corresponding to a figure of merit (FoM) of -250.5 dB.