藉由多層石墨烯工藝優化二硫化鉬電晶體之特性

Abstract

本研究主要探討運用感應式耦合電漿輔助沉積系統於鈷箔基板上合成多層石墨烯，並將其應用於二硫化鉬場效電晶體之製作中。多層石墨烯為半金屬，因具備優異的韌性與材料特性，在本實驗中被選為電極材料，並結合轉移電極技術改善傳統直接蒸鍍金屬於二硫化鉬時所可能引發的材料破壞等問題，有助於改善金屬與半導體界面間費米能階釘札(Fermi Level Pinning)效應所造成的界面電子注入障礙。本研究成功製備石墨烯/二硫化鉬異質結構場效電晶體，石墨烯作為電極轉移至二硫化鉬表面後，能有效調變其介面功函數，進而緩解費米能階釘札效應，有助於提升介面載子注入效率，降低接觸電阻。 元件電性分析顯示，石墨烯電極元件具備明顯的n型導電特性，其導通電流達3.62 × 10−4 A，開關電流比為1.64 × 106，場效遷移率為29.2 cm2/V⋅s，與極低之接觸電阻1.54 kΩ⋅μm，但石墨烯本身具有較高電阻，限制了元件導通電流大小。 本研究使用兩種方式降低石墨烯電阻並提升元件電流： 第一種方式為在石墨烯電極上加上金電極，由於金導電阻較低，因此有效降低電極電阻，導通電流達6.08 × 10−4 A，場效遷移率為48.7 cm2/V⋅s，與低接觸電阻1.95 kΩ⋅μm，展現最好的元件電性結果。 第二種方式為使用插層技術對石墨烯改質，大幅降低電阻。插層石墨烯電極元件同樣能緩解費米能階釘札效應，但插層後接觸電阻升至2.27 kΩ⋅μm。元件電性分析結果顯示，導通電流達提升到了5.37 × 10−4 A，且高遷移率43.5 cm2/V∙s，展現插層技術在犧牲增加接觸電阻情況下，利用電極電阻下降能大幅提升整體的電流。

This study focuses on the synthesis of multilayer graphene on cobalt foil substrates using an ICP-CVD system, and apply in the MoS2 field-effect transistors. Owing to its semimetallic nature, excellent mechanical flexibility, and favorable material properties, multilayer graphene was chosen as the electrode material in this work. To address the issues associated with conventional direct metal deposition on MoS2, such as material degradation and structural damage—a transferred electrode technique was adopted. This method effectively alleviates the Fermi level pinning effect at the metal–semiconductor interface, which commonly leads to carrier injection barriers. A graphene / MoS2 heterostructure FET was successfully fabricated. After transferring the graphene electrode onto the MoS2 surface, the interfacial work function was effectively modulated, thereby mitigating the Fermi level pinning effect. This modulation improves carrier injection efficiency at the interface and leads to a reduction in contact resistance. Electrical measurements of the graphene / MoS2 device revealed clear n type conduction behavior, with an on current of 3.62 × 10−4 A, an on/off current ratio of 1.64 × 106, a field effect mobility of 29.2 cm2/V⋅s, and a low contact resistance of 1.54 kΩ·μm. However, the inherent high resistance of graphene limited the achievable current level of the device. To overcome this limitation and improve device performance, two strategies were employed to reduce the resistance of the graphene electrode. In the first approach, a gold layer was deposited on top of the graphene electrode. Due to the superior conductivity of gold, this structure effectively reduced the overall electrode resistance, resulting in an increased on current of 6.08 × 10−4 A, a field effect mobility of 48.7 cm2/V⋅s, and a contact resistance of 1.95 kΩ⋅μm. In the second approach, graphene was chemically modified through intercalation, which significantly decreased its resistance. Although the intercalated graphene / MoS2 FET also mitigated the Fermi level pinning effect, the increased work function after intercalation led to a higher interfacial barrier, raising the contact resistance to 2.27 kΩ·μm. Nevertheless, the electrical performance of the device improved, with an increased on current of 5.37 × 10-4 A, and an enhanced mobility of 43.5 cm²/V·s. This demonstrates that, despite the increase in contact resistance, the intercalation technique can significantly enhance the overall current by reducing the electrode resistance.