符合 3Dblox 標準之三維積體電路黑盒子階段設計框架與電源分配網路可行性分析

Abstract

隨著二維積體電路（2D-IC）於奈米節點面臨功耗、效能與面積（PPA）之瓶頸，三維積體電路（3D-IC）憑藉其垂直堆疊之結構優勢，成為改善PPA與降低成本的重要技術途徑。然而，目前3D-IC的電子設計自動化（EDA）流程仍處於初期階段，缺乏清晰且結構化的方法學以及完整工具鏈支援；在實務設計中，因涉及多模組堆疊與跨階段協作，整體流程往往複雜、耗時且試錯成本高。 本研究首先提出一套符合系統層至實體實作階段的3D-IC設計流程，為方法學研發與EDA工具整合提供標準化的依據。我們的主要目標，是未來能提供一個往更高抽象階層移動的3D-IC設計流程，使設計者在系統層級即可全面考量系統設計中的各種取捨，以達成系統階層設計之最佳化。 在此目標下，除了實現上述流程的一套原型系統 NTU-3DIC 外，我們亦建構了一個符合 3Dblox 標準之黑盒子階段設計分析與最佳化引擎。本系統提供了直觀的參數化設計介面、清晰的階段劃分與圖形化堆疊視覺支援，並整合黑盒子階段的PDN電壓降（IR-drop）可行性分析與熱區映射功能，協助設計者快速識別潛在熱點並制定相應之優化策略。本研究所提出的設計框架，成功建立一個結構化且可擴展之設計探索與分析架構，不僅顯著提升設計者於設計早期的決策效率，也為後續「shift-left」設計自動化方法以及跨階段EDA工具整合奠定堅實基礎，對推進3D-IC設計的實務與學術研究皆具重要意義。

As two-dimensional integrated circuits (2D-ICs) face power, performance, and area (PPA) bottlenecks at advanced nanometer nodes, three-dimensional integrated circuits (3D-ICs), leveraging vertical stacking structures, have emerged as an essential technological approach to enhance PPA and reduce costs. However, current electronic design automation (EDA) flows for 3D-ICs remain in their early stages, lacking clear, structured methodologies and comprehensive toolchain support. Practical designs typically involve multiple module stacking and cross-phase collaborations, making the overall design process complex, time-consuming, and prone to high trial-and-error costs. In this research, we first propose a structured and standardized 3D-IC design flow that spans from the system level down to the physical implementation stage. This proposed design flow serves as a foundational methodology for future research and integration with EDA tools. The primary objective of our study is to facilitate the shift of 3D-IC design toward higher abstraction levels, enabling designers to consider comprehensive system-level trade-offs early on and achieve system-level design optimization effectively. Toward this goal, in addition to implementing a prototype system called NTU-3DIC based on our proposed flow, we also develop an analysis and optimization engine compliant with the 3Dblox standard for blackbox-stage design exploration. The prototype features an intuitive parametric design interface, clearly defined design stages, and graphical stacking visualization capabilities. It also integrates feasibility analysis of PDN voltage drop (IR-drop) and hotspot mapping during the blackbox stage, assisting designers in rapidly identifying potential thermal hotspots and formulating corresponding optimization strategies. The proposed design methodology successfully establishes a structured and extensible design exploration and analysis framework. It significantly enhances early-stage decision-making efficiency for designers and provides a robust foundation for subsequent "shift-left" design automation approaches and cross-phase EDA tool integration, thus advancing both practical and academic development in the field of 3D-IC design.