應用於第七代無線網路及毫米波雷達寬頻CMOS低雜訊放大器與應用於 6G 通訊之 GaAs HBT 功率放大器研究

Abstract

本論文主要可分為三個部分。 第一部分介紹一款採用 TSMC 90 nm 製程設計的第七代無線網路寬頻低雜訊放大器。在接收系統中，低雜訊放大器需兼具低雜訊指數與高增益的特性。為達成此目標，本論文所提出的設計於輸入端採用最佳化的路徑匹配網路，並結合電容性與電感性磁耦合共振腔，構建寬頻匹配架構以實現寬頻雜訊匹配；輸出端也採用磁耦合共振腔架構達成寬頻增益匹配。根據量測結果，該電路在 4.04 GHz 至 6.3 GHz 頻段內，達成 43.7% 的 3 dB 帶寬，最大增益可達 16.6 dB，最低雜訊指數則為 2.1 dB，展現優異的性能表現。 第二部分則提出一款適用於雷達通訊的 V-Band 低雜訊放大器。該電路採用 UMC 40 nm CMOS 製程實現，結合源極退化技術與 gm boosting，有效提升放大器的整體性能。模擬結果顯示，該 LNA 在 57 GHz 至 71 GHz 頻段內具備約 20 dB 的小訊號增益，3 dB 頻寬涵蓋整個 V-Band，且雜訊指數極低，展現出卓越的寬頻與低雜訊特性。 第三部分則聚焦於 FR3 頻段（約 13 GHz）應用所設計的 GaAs HBT 功率放大器。該設計強調一級一路架構的優化，採用高功率密度的 HBT 晶體管，並結合熱模擬結果進行電路與佈局優化，以提升功率附加效率（PAE）與熱穩定性。量測結果顯示，一級一路放大器在 12.3 GHz 時達到 32.0 dBm 的輸出功率、51% 的 PAE 以及約 10.5 dB 的增益；兩級一路放大器則分別達到 32.2 dBm 輸出功率、54.5% PAE 及約 21.7 dB 增益；兩級兩路放大器則可達 34.4 dBm 輸出功率、50% PAE 與約 21.1 dB 增益，展現優異的大訊號性能。本部分亦探討了 Flip-Chip 封裝技術在 HBT 功率放大器中的應用，並分析功率耗散與熱阻對接面溫度及晶體管特性的影響。實驗結果顯示，導入銅柱技術後，於 12 GHz 頻點 PAE 提升達 24.9%，輸出功率與增益分別增加 1.1 dB 與 0.9 dB，有效強化了高頻大訊號表現與電路可靠度。

This paper is mainly divided into three parts. The first part introduces a seventh-generation wideband low-noise amplifier (LNA) designed using the TSMC 90 nm process. In receiver systems, the LNA needs to simultaneously achieve low noise figure and high gain. To meet these requirements, the proposed design employs an optimized path-matching network at the input, combined with capacitive and inductive magnetically coupled resonators to build a wideband noise-matching architecture. The output also utilizes a magnetically coupled resonator structure to achieve wideband gain matching. Measurement results show that the circuit attains a 3 dB bandwidth of 43.7% over the frequency range of 4.04 GHz to 6.3 GHz, with a maximum gain of 16.6 dB and a minimum noise figure of 2.1 dB, demonstrating excellent performance. The second part proposes a V-Band LNA suitable for radar communication applications. This circuit is implemented in UMC 40 nm CMOS technology and incorporates source degeneration and gm boosting techniques to effectively enhance the overall amplifier performance. Simulation results indicate that the LNA provides approximately 20 dB small-signal gain across the 57 GHz to 71 GHz band, covering the entire V-Band with a 3 dB bandwidth, and exhibits an extremely low noise figure, demonstrating outstanding wideband and low-noise characteristics. The third part focuses on the design of a GaAs HBT power amplifier for the FR3 band (around 13 GHz). This design emphasizes optimization of a single-stage single-path architecture, utilizing high power density HBT devices and incorporating thermal simulation results to optimize the circuit and layout, thereby improving power-added efficiency (PAE) and thermal stability. Measurement results show that the single-stage single-path amplifier achieves an output power of 32.08 dBm, a PAE of 51%, and a gain of approximately 10.5 dB at 12.3 GHz; the two-stage single-path amplifier achieves 32.28 dBm output power, 54.5% PAE, and about 21.73 dB gain; the two-stage dual-path amplifier achieves 34.4 dBm output power, 50% PAE, and about 21.09 dB gain, demonstrating excellent large-signal performance. This part also explores the application of Flip-Chip packaging technology in HBT power amplifiers and analyzes the impact of power dissipation and thermal resistance on the interface temperature and transistor characteristics. Experimental results indicate that, after introducing copper pillar technology, the PAE at 12 GHz improved by 24.9%, with output power and gain increasing by 1.1 dB and 0.9 dB respectively, effectively enhancing high-frequency large-signal performance and circuit reliability.