考量預放置元件之多目標的多位元正反器電路擺置

Abstract

在現代積體電路（IC）設計中，將單位元正反器（single-bit flip-flops, SBFFs）合併為多位元正反器（multi-bit flip-flops, MBFFs）可有效降低功耗及面積。然而，在多位元正反器的合併與合法化過程中，若發生過度位移，則可能導致嚴重的時序劣化。為解決此問題，本論文提出首個考量預放置元件所引起過度位移的完整多位元正反器擺置方法，並兼顧時序、功耗與面積等多目標最佳化。所提出的方法包含三個核心關鍵：（1）一個時序導向的力模型，以微調正反器位置並提供更佳的多位元正反器合併；（2）一個合併與合法化的混合流程，以降低位移導致的時序劣化；（3）一個多目標函數，以挑選適合進行多位元正反器合併之正反器候選者。本方法在2024年國際積體電路電腦輔助設計軟體製作競賽（2024 CAD Contest at ICCAD）之「利用多位元正反器之功耗與時序最佳化（Power and Timing Optimization Using Multibit Flip-Flop）」問題，於所有參賽隊伍中獲得最佳成績，展現出本方法於電路優化上的有效性。

In modern integrated circuit (IC) design, clustering single-bit flip-flops (SBFFs) into multi-bit flip-flops (MBFFs) can effectively reduce power consumption and area. However, excessive displacement during the MBFF clustering and legalization process may incur significant timing degradation. To address this issue, this thesis proposes the first comprehensive MBFF placement methodology that considers excessive displacement caused by pre-placed cells, while simultaneously optimizing multiple objectives, including timing, power, and area. The proposed methodology consists of three key components: (1) a timing-driven force model to relocate flip-flops and enable better MBFF clustering; (2) a clustering-legalization hybrid flow to reduce timing degradation caused by displacement; (3) a multi-objective function to identify flip-flop candidates suitable for MBFF clustering. Our methodology achieved the best results among all participating teams at the 2024 CAD Contest at ICCAD on Power and Timing Optimization Using Multibit Flip-Flop, demonstrating its effectiveness in circuit optimization.