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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 李承彥 | zh_TW |
| dc.contributor.author | Cheng-Yen Li | en |
| dc.date.accessioned | 2025-08-19T16:08:55Z | - |
| dc.date.available | 2025-08-20 | - |
| dc.date.copyright | 2025-08-19 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-08 | - |
| dc.identifier.citation | [1] 2024 CAD contest at ICCAD. [Online]. Available: https://www.iccad-contest.org/2024/
[2] 2025 CAD contest at ICCAD. [Online]. Available: https://www.iccad-contest.org/2025/ [3] Y. Cai, L. Zhu, and X. Guo, “Revisit MBFF: Efficient early-stage multi-bit flip-flops clustering with physical and timing awareness,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 1230–1236, Tokyo, Japan, January 2025. [4] Y.-C. Chang, T.-W. Lin, I. H.-R. Jiang, and G.-J. Nam, “Graceful register clustering by effective mean shift algorithm for power and timing balancing,” in Proceedings of ACM International Symposium on Physical Design, pp. 11–18, New York, NY, USA, April 2019. [5] Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsai, and S.-F. Chen, “Post-placement power optimization with multi-bit flip-flops,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 218–223, San Jose, CA, USA, November 2010. [6] Y.-Y. Chen, H.-Y. Wu, I. H.-R. Jiang, C.-H. Tsai, and C.-C. Wu, “Slack redistributed register clustering with mixed-driving strength multi-bit flip-flops,” in Proceedings of ACM International Symposium on Physical Design, pp. 21–29, New York, NY, USA, March 2024. [7] J. Friedman, J. Bentley, and R. Finkel, “An algorithm for finding best matches in logarithmic expected time,” ACM Transactions on Mathematical Software, vol. 3, no. 3, pp. 209–226, September 1977. [8] Y.-T. Hsieh, T.-W. Lin, Y.-C. Chang, H.-Y. Wu, and I. H.-R. Jiang, “Graceful register clustering and rebanking for power and timing balancing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 3, pp. 1070–1083, March 2025. [9] I. H.-R. Jiang, C.-L. Chang, and Y.-M. Yang, “INTEGRA: Fast multibit flip-flop clustering for clock power saving,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 192–204, February 2012. [10] A. Kahng, S. Kundu, and S. Thumathy, “Scalable flip-flop clustering using divide and conquer for capacitated k-means,” in Proceedings of the Great Lakes Symposium on VLSI, pp. 177–184, New York, NY, USA, June 2024. [11] M. P.-H. Lin, C.-C. Hsu, and Y.-C. Chen, “Clock-tree aware multibit flip-flop generation during placement for power optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 2, pp. 280–292, February 2015. [12] S. S.-Y. Liu, W.-T. Lo, C.-J. Lee, and H.-M. Chen, “Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization,” ACM Transactions on Design Automation of Electronic Systems, vol. 18, no. 3, pp. 1–20, July 2013. [13] Y.-C. Lu, Z. Guo, K. Kunal, R. Liang, and H. Ren, “INSTA: An ultra-fast, differentiable, statistical static timing analysis engine for industrial physical design applications,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–7, San Francisco, CA, USA, June 2025. [14] H. Moon and T. Kim, “Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 268–273, Macao, China, January 2016. [15] I. Seitanidis, G. Dimitrakopoulos, P. M. Mattheakis, L. Masse-Navette, and D. Chinnery, “Timing-driven and placement-aware multibit register composition,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 8, pp. 1501–1514, August 2019. [16] Synopsys, Inc. Fusion compiler: RTL-to-GDSII design solution. [Online]. Available: https://www.synopsys.com/implementation-and-signoff/physical-implementation/fusion-compiler.html [17] C.-C. Tsai, Y. Shi, G. Luo, and I. H.-R. Jiang, “FF-bond: multi-bit flip-flop bonding at placement,” in Proceedings of ACM International Symposium on Physical Design, pp. 147–153, Stateline, Nevada, USA, March 2013. [18] S.-H. Wang, Y.-Y. Liang, T.-Y. Kuo, and W.-K. Mak, “Power-driven flip-flop merging and relocation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 180–191, February 2012. [19] G. Wu, Y. Xu, D. Wu, M. Ragupathy, Y.-y. Mo, and C. Chu, “Flip-flop clustering by weighted K-means algorithm,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, Austin, TX, USA, June 2016. [20] S.-W. Yang, J.-W. Hsu, T. W. Li, T.-H. Chen, and C.-F. C. Shen, “2024 ICCAD CAD contest problem B: Power and timing optimization using multibit flip-flop,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–6, Newark, NJ, USA, October 2024. [21] D. Yi and T. Kim, “Allocation of multi-bit flip-flops in logic synthesis for power optimization,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–6, Austin, TX, USA, November 2016. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98773 | - |
| dc.description.abstract | 在現代積體電路（IC）設計中，將單位元正反器（single-bit flip-flops, SBFFs）合併為多位元正反器（multi-bit flip-flops, MBFFs）可有效降低功耗及面積。然而，在多位元正反器的合併與合法化過程中，若發生過度位移，則可能導致嚴重的時序劣化。為解決此問題，本論文提出首個考量預放置元件所引起過度位移的完整多位元正反器擺置方法，並兼顧時序、功耗與面積等多目標最佳化。所提出的方法包含三個核心關鍵：（1）一個時序導向的力模型，以微調正反器位置並提供更佳的多位元正反器合併；（2）一個合併與合法化的混合流程，以降低位移導致的時序劣化；（3）一個多目標函數，以挑選適合進行多位元正反器合併之正反器候選者。本方法在2024年國際積體電路電腦輔助設計軟體製作競賽（2024 CAD Contest at ICCAD）之「利用多位元正反器之功耗與時序最佳化（Power and Timing Optimization Using Multibit Flip-Flop）」問題，於所有參賽隊伍中獲得最佳成績，展現出本方法於電路優化上的有效性。 | zh_TW |
| dc.description.abstract | In modern integrated circuit (IC) design, clustering single-bit flip-flops (SBFFs) into multi-bit flip-flops (MBFFs) can effectively reduce power consumption and area. However, excessive displacement during the MBFF clustering and legalization process may incur significant timing degradation. To address this issue, this thesis proposes the first comprehensive MBFF placement methodology that considers excessive displacement caused by pre-placed cells, while simultaneously optimizing multiple objectives, including timing, power, and area. The proposed methodology consists of three key components: (1) a timing-driven force model to relocate flip-flops and enable better MBFF clustering; (2) a clustering-legalization hybrid flow to reduce timing degradation caused by displacement; (3) a multi-objective function to identify flip-flop candidates suitable for MBFF clustering. Our methodology achieved the best results among all participating teams at the 2024 CAD Contest at ICCAD on Power and Timing Optimization Using Multibit Flip-Flop, demonstrating its effectiveness in circuit optimization. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-19T16:08:55Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-19T16:08:55Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi Table of Contents vii List of Tables ix List of Figures x Chapter 1. Introduction 1 1.1 Multi-Bit Flip-Flop Clustering and Declustering . . . . . . . . . . . . . . 1 1.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2. Preliminaries 9 2.1 MBFF Clustering Stages in the Design Flow . . . . . . . . . . . . . . . . 9 2.1.1 Pre-Placement MBFF Clustering . . . . . . . . . . . . . . . . . . . 9 2.1.2 In-Placement MBFF Clustering . . . . . . . . . . . . . . . . . . . . 10 2.1.3 Post-Placement MBFF Clustering . . . . . . . . . . . . . . . . . . 10 2.1.4 Summary and Comparison . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 3. Our Proposed Methodology 14 3.1 Flip-Flop and Cell Library Preprocessing . . . . . . . . . . . . . . . . . . 15 3.2 MBFF Clustering and Placement . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 Flip-Flop Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.2 k-Bit Flip-Flop Clustering . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 k-Bit Flip-Flop Legalization . . . . . . . . . . . . . . . . . . . . . . 23 3.2.4 k-Bit Flip-Flop Candidate Selection . . . . . . . . . . . . . . . . . 27 3.2.5 MBFF Declustering . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Chapter 4. Experimental Results 31 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 Benchmark Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 Score Comparison of the Top Three Teams and Ours . . . . . . . . 34 4.3.2 Analysis of Detailed Metrics . . . . . . . . . . . . . . . . . . . . . 36 4.3.3 Analysis of Clustering Ratio . . . . . . . . . . . . . . . . . . . . . 38 4.4 Effectiveness of Proposed Methodology . . . . . . . . . . . . . . . . . . . 41 4.5 Layout Visualizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 5. Conclusions and Future Work 47 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2.1 Enhancing MBFF Selection Strategies . . . . . . . . . . . . . . . . 48 5.2.2 Improving Integration with Real Designs and Tools . . . . . . . . . 49 5.2.3 Expanding to More Objectives . . . . . . . . . . . . . . . . . . . . 50 5.2.4 Leveraging GPU Acceleration . . . . . . . . . . . . . . . . . . . . . 50 Bibliography 52 Publication List 56 | - |
| dc.language.iso | en | - |
| dc.subject | 時序 | zh_TW |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 合法化 | zh_TW |
| dc.subject | 擺置 | zh_TW |
| dc.subject | 多位元正反器 | zh_TW |
| dc.subject | Multi-Bit Flip-Flop | en |
| dc.subject | Placement | en |
| dc.subject | Legalization | en |
| dc.subject | Timing | en |
| dc.subject | Physical Design | en |
| dc.title | 考量預放置元件之多目標的多位元正反器電路擺置 | zh_TW |
| dc.title | Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃婷婷;方劭云;江蕙如 | zh_TW |
| dc.contributor.oralexamcommittee | Ting-Ting Hwang;Shao-Yun Fang;Iris Hui-Ru Jiang | en |
| dc.subject.keyword | 實體設計,時序,多位元正反器,擺置,合法化, | zh_TW |
| dc.subject.keyword | Physical Design,Timing,Multi-Bit Flip-Flop,Placement,Legalization, | en |
| dc.relation.page | 56 | - |
| dc.identifier.doi | 10.6342/NTU202503564 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2025-08-13 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2025-08-20 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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