6T與8T鰭式場效電晶體之低溫靜態隨機存取記憶體最佳化

Abstract

將互補式金氧半場效電晶體（Complementary Metal-Oxide Semiconductor, CMOS）操作於低溫環境，有助於實現高效能運算（High-Performance Computing, HPC）。然而，如何在低臨界電壓（Vt）設計下維持靜態隨機存取記憶體（Static Random-Access Memory, SRAM）的穩定性仍是一大挑戰。本研究針對低溫6T與8T-SRAM的特性進行系統性分析，並提出優化設計方案，以同時強化其穩定性與操作效能。 對77 K下6T-SRAM單元，本研究提出兩種優化穩定性Vt設計：(1) 標準供應電壓（0.75 V）下之6T-ES（Enhanced Speed）方案，相較於LVT（|Vt| = 0.15 V）設計，可提升3.4倍的讀取靜態雜訊邊界（Read Static Noise Margin, RSNM）；(2) 低電壓（0.4 V）下之6T-LP（Low Power）方案，透過強化上拉電晶體（Pull-Up, PU）設計，可提升讀取穩定性，同時不犧牲讀取速度與寫入能力。於關鍵製程角落（Process Corner）下，6T-LP可將RSNM提升至LVT設計的1.3倍。 本研究亦分析低溫電流閂鎖感測放大器（Current-Latched Sense Amplifier, CLSA）與電壓閂鎖感測放大器（Voltage-Latched Sense Amplifier, VLSA）。考量冷卻能量（Cooling Energy）後，77 K下CLSA與VLSA皆採用較低的VDD（0.4 V）與LVT設計，CLSA可維持與室溫操作相當的能量效率（Energy Delay Product, EDP），而VLSA則因具備顯著的速度提升，可進一步降低約20%的EDP。 8T-SRAM單元由於具備讀寫路徑分離架構，本身具有較佳的讀取穩定性，本研究進一步提出Vt設計策略，優化其在低VDD（0.4 V）下的穩定性與讀取效能。針對77 K下6N2P與4N4P架構，分別提出8T-6N2P-LP與8T-4N4P-LP之Vt設計方案。相較於採用LVT設計之6T-SRAM，8T-6N2P-LP與8T-4N4P-LP在關鍵製程角落下之RSNM可提升6.3倍。此外，將4N4P讀出電路 (Readout Circuit) 之供應電壓（VSEN）由0.4 V降低至0.3 V（LRV-8T-4N4P-LP），可額外縮短8%的讀取時間。綜合上述研究成果，本論文提出之設計策略展現具備提升低溫SRAM應用於HPC系統之潛力，為未來低溫積體電路設計提供重要參考依據與實用方法。

Cryogenic complementary metal-oxide semiconductor (Cryo-CMOS) technology offers promising potential for enabling high-performance computing (HPC). However, maintaining the stability of static random-access memory (SRAM) under low threshold voltage (Vt) design remains a significant challenge. This study systematically analyzes the characteristics of 6T and 8T-SRAM under cryogenic operation and proposes optimized design strategies to simultaneously enhance both stability and performance. For 6T-SRAM at 77 K, two Vt optimization designs are proposed: (1) the 6T-ES (Enhanced Speed) design for nominal VDD = 0.75 V, which improves the read static noise margin (RSNM) by 3.4× compared to the LVT design (|Vt| = 0.15 V). (2) the 6T-LP (Low Power) design for reduced VDD = 0.4 V, which strengthens the pull-up (PU) transistors to enhance read stability without sacrificing read and write capability. Under critical process corners, the 6T-LP achieves up to 1.3× RSNM improvement over the LVT baseline. In addition, this study evaluates the performance of cryogenic current-latched sense amplifier (CLSA) and voltage-latched sense amplifier (VLSA). Considering cooling energy, CLSA and VLSA adopt low VDD (0.4 V) and LVT design at 77 K. The cryogenic CLSA maintains a comparable energy delay product (EDP) to its room-temperature counterpart, while the cryogenic VLSA achieves approximately 20% lower EDP due to significant speed improvement. Owing to the decoupled read/write paths, 8T-SRAM inherently provides better read stability. This work proposes Vt design strategies for 6N2P and 4N4P 8T-SRAM to optimize their stability and read performance under low VDD (0.4 V) conditions. Compared to 6T-SRAM with an LVT design at 77 K, the proposed 8T designs enhance RSNM by up to 6.3× under critical process corners. Furthermore, reducing the supply voltage (VSEN) of 4N4P readout circuit from 0.4 V to 0.3 V (LRV-8T-4N4P-LP) shortens the read time by an additional 8%. In summary, the proposed design strategies significantly enhance the stability and performance of cryogenic SRAM, demonstrating strong potential for HPC applications and providing valuable guidance for future cryogenic IC design.