通過環路濾波器優化與電荷泵匹配降低相位檢測器抖動

Abstract

隨著資料通訊系統向更高速度和更高可靠性發展，低抖動時脈和資料復原(CDR)電路的設計變得愈發重要。在眾多架構中，利用不同類型相位偵測器(PD)的鎖相環(PLL)在時脈同步中扮演關鍵角色。 Hogge PD是基於線性工作，具有較低的抖動，但容易受到振幅雜訊和失配的影響。相較之下，Bang-Bang相位檢測器(BBPD)，如Alexander PD，具有高度數位化的特點，適合低功耗和緊湊設計，但由於其二進位相位比較機制，通常會引入更高的抖動。 最近的研究表明，透過調整環路濾波器和增強電荷泵電流匹配，優化PD架構有望將抖動降低到相當的水平。本論文旨在探討基於台積電(TSMC)180nm CMOS製程的2Gb/s NRZ訊號系統的最佳化技術。在高速資料通訊系統中，時脈和資料復原(CDR)電路在資料流同步中至關重要。相位檢測器 (PD) 是CDR電路的關鍵組件，對抖動性能有顯著影響。 Hogge PD因其線性工作和低抖動而受到廣泛認可，但需要精確的模擬前端設計。相對而言，Bang-Bang相位檢測器(BBPD)，如Alexander PD，因其易於數位實現而頗具吸引力，儘管由於極限環行為導致抖動較高。 隨著對緊湊型和節能係統需求的增加，PD正受到越來越多的關注。本論文透過優化環路濾波器和電荷泵，探討了HPD與BBPD的低抖動PD設計。

The evolution of data communication systems toward higher speeds and enhanced reliability has intensified the demand for low-jitter clock and data recovery (CDR) circuits. Among diverse architectures, phase-locked loops (PLLs) employing heterogeneous phase detectors (PDs) play a pivotal role in clock synchronization. Hogge PDs, operating on linear principles, deliver superior jitter performance but exhibit heightened susceptibility to amplitude noise and matching imperfections. Conversely, bang-bang phase detectors (BBPDs) such as the Alexander topology offer compelling advantages in power efficiency and footprint reduction through fully digital implementation, albeit introducing elevated jitter due to binary quantization mechanisms. Emerging research indicates that co-optimization of loop filter characteristics and charge pump current matching can potentially equalize jitter performance across PD architectures. This investigation focuses on design optimization for 2-Gbps NRZ systems in TSMC's 180nm CMOS technology. Within high-speed data links, CDR circuits are fundamental for stream synchronization, where phase detectors critically influence jitter behavior. While the linear transfer characteristic of Hogge PDs ensures widespread adoption, it necessitates precision analog front-end design. Digital-intensive BBPDs facilitate integration but suffer from high-frequency jitter induced by limit-cycle oscillation. Amid growing requirements for compact and energy-efficient systems, PD design has gained renewed attention. Our methodology achieves jitter minimization in both Hogge and Bang-Bang implementations through loop filter parameter tuning and charge pump mismatch compensation techniques.