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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98420完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | zh_TW |
| dc.contributor.advisor | Charlie Chung-Ping Chen | en |
| dc.contributor.author | 何迪倫 | zh_TW |
| dc.contributor.author | DYLAN HO | en |
| dc.date.accessioned | 2025-08-05T16:18:20Z | - |
| dc.date.available | 2025-08-06 | - |
| dc.date.copyright | 2025-08-05 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-07-29 | - |
| dc.identifier.citation | B. Razavi, “Monolithic phase-locked loops and clock recovery circuits: Theory and design,” IEEE Press, pp. 381–381, 1996.
B. Razavi, “Challenges in the design high-speed clock and data recovery circuits,” IEEE Communications Magazine, vol. 40, no. 8, pp. 94–101, 2002. B. Razavi, “The design of broadband i/o circuits [the analog mind],” IEEE Communications Magazine, vol. 13, no. 2, pp. 6–15, 2021. C. Hogge, “A self correcting clock recovery circuit,” IEEE Transactions on Electron Devices, vol. 32, no. 12, pp. 2704–2706, 1985. B. Razavi, “Clock recovery from random binary signals,” Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, pp. 242–243, 1996. e. a. J. S. Lee, “Charge pump with perfect current matching characteristics in phase-locked loops,” IET Electronics Letters, vol. 36, no. 23, pp. 1907–1908, 2000. H. W. L. R. J. Baker and D. E. Boyce, “Cmos: Circuit design, layout, and simulation,” IEEE Press, Piscataway, NJ 1998. A. Samuel and J. de Gyvez, “A multi-band single-loop pll frequency synthesizer with dynamically-controlled switched tuning vco,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), vol. 2, pp. 818–821 vol.2, 2000. S. Nagata, E. Martens, A. Cooman, and J. Craninckx, “A 28ghz low jitter, low power fully differential self-biased clock buffer with embedded low pass filter utilizing enable switch in 16nm finfet,” 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 895–899, 2023. A. Verma and B. P. Das, “A low power dual-band sub-sampling phase locked loop with sub-100 fs rms jitter and <-255-db fomjitter,” 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems(VLSID), pp. 156–161, 2024. J. Kim, J. Bang, S. Jung, M. Han, and J. Choi, “A low-reference-spur and low-jitter d-band pll with complementary power-gating injection-locked frequency-multiplier-based phase detector,” IEEE Solid-State Circuits Letters, vol. 8, pp. 129–132, 2025. H. Ren, Y. Huang, Z. Yang, T. Chen, X. Meng, W. Yan, W. Zhang, Z. Li, T. Iizuka, P.-I. Mak, Y. Chen, and B. Li, “A type-ii reference-sampling pll with non-uniform octuple-sampling phase detector achieving 55-fs jitterrms,–91.9-dbc reference spur and –259-db jitter-power fom,” 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 113–116, 2024. M. A. Tiruye, O. B. Gerba, and T. H. Teo, “A 155 mhz low-jitter pll for enhanced signal integrity in high-speed interconnects,” 2024 IEEE 33rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 1–3, 2024. J. Gong, E. Charbon, F. Sebastiano, and M. Babaie, “A low-jitter and low-spur charge-sampling pll,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 492–504, 2022. C.-C. Chang, Y.-T. Chin, H. A. Ibrahim, K. Y. Chang, and S.-J. Jou, “A low-jitter adpll with adaptive high-order loop filter and fine grain varactor based dco,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2021. Y. Xing, J. Song, J. Lei, and M. Ren, “A dual-loop charge pump phase-locked loop based on 130nm cmos process with output frequency range of 0.5ghz 2ghz,” 2024 6th International Conference on Electronic Engineering and Informatics (EEI), pp. 261–266, 2024. D. A. Pontes, H. D. Hernandez, D. Reyes, and L. E. Rueda, “A 1.6-ghz low-jitter, low reference-spur single-loop type-i pll,” 2021 International Conference on Electrical, Computer and Energy Technologies (ICECET), pp. 1–4, 2021. J. Hu, Z. Huang, B. Duan, Q. Li, Z. Song, and D. He, “A multiplying delay-locked loop design with low jitter and high linearity,” 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), pp. 38–39, 2022. C.-F. Liang, H.-L. Chu, and S.-I. Liu, “10-gb/s inductorless cdrs with digital frequency calibration,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 9, pp. 2514–2524, 2008. S.-H. Lin and S.-I. Liu, “Full-rate bang-bang phase/frequency detectors for unilateral continuous-rate cdrs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 12, pp. 1214–1218, 2008. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98420 | - |
| dc.description.abstract | 隨著資料通訊系統向更高速度和更高可靠性發展，低抖動時脈和資料復原(CDR)電路的設計變得愈發重要。在眾多架構中，利用不同類型相位偵測器(PD)的鎖相環(PLL)在時脈同步中扮演關鍵角色。 Hogge PD是基於線性工作，具有較低的抖動，但容易受到振幅雜訊和失配的影響。相較之下，Bang-Bang相位檢測器(BBPD)，如Alexander PD，具有高度數位化的特點，適合低功耗和緊湊設計，但由於其二進位相位比較機制，通常會引入更高的抖動。
最近的研究表明，透過調整環路濾波器和增強電荷泵電流匹配，優化PD架構有望將抖動降低到相當的水平。本論文旨在探討基於台積電(TSMC)180nm CMOS製程的2Gb/s NRZ訊號系統的最佳化技術。在高速資料通訊系統中，時脈和資料復原(CDR)電路在資料流同步中至關重要。相位檢測器 (PD) 是CDR電路的關鍵組件，對抖動性能有顯著影響。 Hogge PD因其線性工作和低抖動而受到廣泛認可，但需要精確的模擬前端設計。相對而言，Bang-Bang相位檢測器(BBPD)，如Alexander PD，因其易於數位實現而頗具吸引力，儘管由於極限環行為導致抖動較高。 隨著對緊湊型和節能係統需求的增加，PD正受到越來越多的關注。本論文透過優化環路濾波器和電荷泵，探討了HPD與BBPD的低抖動PD設計。 | zh_TW |
| dc.description.abstract | The evolution of data communication systems toward higher speeds and enhanced reliability has intensified the demand for low-jitter clock and data recovery (CDR) circuits. Among diverse architectures, phase-locked loops (PLLs) employing heterogeneous phase detectors (PDs) play a pivotal role in clock synchronization. Hogge PDs, operating on linear principles, deliver superior jitter performance but exhibit heightened susceptibility to amplitude noise and matching imperfections. Conversely, bang-bang phase detectors (BBPDs) such as the Alexander topology offer compelling advantages in power efficiency and footprint reduction through fully digital implementation, albeit introducing elevated jitter due to binary quantization mechanisms.
Emerging research indicates that co-optimization of loop filter characteristics and charge pump current matching can potentially equalize jitter performance across PD architectures. This investigation focuses on design optimization for 2-Gbps NRZ systems in TSMC's 180nm CMOS technology. Within high-speed data links, CDR circuits are fundamental for stream synchronization, where phase detectors critically influence jitter behavior. While the linear transfer characteristic of Hogge PDs ensures widespread adoption, it necessitates precision analog front-end design. Digital-intensive BBPDs facilitate integration but suffer from high-frequency jitter induced by limit-cycle oscillation. Amid growing requirements for compact and energy-efficient systems, PD design has gained renewed attention. Our methodology achieves jitter minimization in both Hogge and Bang-Bang implementations through loop filter parameter tuning and charge pump mismatch compensation techniques. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-05T16:18:20Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-05T16:18:20Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements ii
摘要 iv Abstract vi Contents ix List of Figures xiii List of Tables xv Chapter 1 Introduction 1 1.1 Backgrounds 1 1.2 Thesis Organization 1 1.3 Overview of the CDR Application 2 Chapter 2 Phase Detector Schemes 4 2.1 Hogge Phase Detector (HPD) 4 2.2 Bang-Bang Phase Detector (BBPD) 7 Chapter 3 Basic Analysis of Circuit Architecture 11 3.1 Charge Pump vs. Charge Pump with Feedback 11 3.1.1 Conventional Charge Pump: Mismatch Analysis 12 3.1.2 Feedback Charge Pump: Dynamic Matching 14 3.2 Loop Filter Optimization 18 3.2.1 Loop Filter Optimization for High-Frequency Ripple Suppression 18 3.2.2 Loop Filter C₂ Optimization Trade-offs 21 3.3 Ring VCO vs. LC VCO 23 3.3.1 LC Voltage-Controlled Oscillator Design 23 3.3.2 Limitations of Ring Oscillator Topology 26 3.3.3 Phase Noise Optimization in LC-VCO 29 Chapter 4 Reducing Jitter in Phase Detectors by Optimizing Loop Filters and Matching Charge Pumps 31 4.1 HPD for CDR Circuit Implementation 31 4.2 Clock-Data Frequency Locking Principle 33 4.3 Circuit Response to Stress Patterns 35 4.4 HPD for CDR Circuit Simulated Result 37 4.5 BBPD for CDR Circuit Implementation 40 4.6 BBPD for CDR Circuit Simulated Result 41 Chapter 5 Summary 45 5.1 Conclusion 45 5.2 Future Work 46 References 48 Appendix A — Background Knowledge 51 A.1 Transformation Relationship Between Discrete and Continuous Do-main Autocorrelation 51 A.2 Physical Significance of Unipolar-to-Bipolar Conversion 52 A.3 Derivation Process of Autocorrelation Spectrum 53 A.4 Phase Error Analysis in Charge Pump 54 A.5 Random Bitstream Generator (Veriloga Code) 55 A.6 Divider (Veriloga Code) 57 | - |
| dc.language.iso | en | - |
| dc.subject | 鎖相環 | zh_TW |
| dc.subject | 線性相位偵測器 | zh_TW |
| dc.subject | 二位元相位偵測器 | zh_TW |
| dc.subject | 抖動優化 | zh_TW |
| dc.subject | 迴路濾波器 | zh_TW |
| dc.subject | 電荷泵匹配 | zh_TW |
| dc.subject | Bang-Bang PD | en |
| dc.subject | PLL | en |
| dc.subject | Charge Pump Matching | en |
| dc.subject | Loop Filter | en |
| dc.subject | Jitter Optimization | en |
| dc.subject | Hogge PD | en |
| dc.title | 通過環路濾波器優化與電荷泵匹配降低相位檢測器抖動 | zh_TW |
| dc.title | Reducing Jitter in Phase Detectors by Optimizing Loop Filters and Matching Charge Pumps | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 曹恆偉;錢膺仁 | zh_TW |
| dc.contributor.oralexamcommittee | Hen-Wai Tsao;Ying-Ren Chien | en |
| dc.subject.keyword | 鎖相環,線性相位偵測器,二位元相位偵測器,抖動優化,迴路濾波器,電荷泵匹配, | zh_TW |
| dc.subject.keyword | PLL,Hogge PD,Bang-Bang PD,Jitter Optimization,Loop Filter,Charge Pump Matching, | en |
| dc.relation.page | 59 | - |
| dc.identifier.doi | 10.6342/NTU202502916 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-07-31 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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