一 10 位元雙階段數位類比轉換器之具備電流分流轉導調變與 4 位元數位類比轉換嵌入式運算放大器

Abstract

本論文提出一具備高線性度、低功耗且具備緊湊面積的10 位元雙階段式數位類比轉換器。隨著現代電子產品朝向高整合度、高精度與低功耗方向發展，數位類比轉換器在整體系統中扮演關鍵角色，對於其解析度、線性度、面積效率與功耗等方面的性能需求也日益嚴苛。 為因應上述挑戰，本研究採用雙階段架構，以兼顧解析度與面積效率。第一級為6 位元電阻串式數位類比轉換器，第二級則為嵌入4 位元數位類比轉換器的運算放大器，以提升整體面積效率。此外，於第二級中導入電流分流轉導調變技術，進一步提升線性度，同時不引入額外的靜態功耗。 本晶片使用台積電180 奈米互補式金氧半製程製程實現，單通道面積為13787 μm^2。根據量測結果，數位類比轉換器穩態時間為3.6 μs，最大差分非線性與積分非線性分別為1.81 LSB 與1.72 LSB，其中1 LSB 對應3.125 mV 。該電路的功耗為298 μW，整體性能符合現代高性能數位類比轉換器需求。

This thesis proposes a compact, linear, and power-efficient 10-bit two-stage digital-to-analog converter (DAC). As modern electronic systems evolve toward higher integration, precision, and energy efficiency, the performance demands on DACs have become increasingly stringent, such as resolution, linearity, area efficiency, and power consumption. To address these challenges, the proposed DAC adopts a two-stage architecture, with the first stage consisting of a 6-bit resistor DAC (RDAC) and the second stage comprising a 4-bit DAC-embedded operational amplifier (Op-Amp), improving area efficiency. Additionally, a current spillover gm-modulation technique is incorporated into the second stage DAC to further improve linearity without introducing additional static power consumption. The proposed DAC is fabricated in TSMC 180nm CMOS technology with a channel area of 13787 μm^2. The settling time of the proposed DAC is 3.6 μs. The maximum differential nonlinearity (DNL) and integral nonlinearity (INL) were measured as 1.81 and 1.72 LSB, respectively, with 1 LSB = 3.125 mV. The power consumption of the proposed DAC is 298 μW.