碳化矽金氧半結構之二氧化矽氧化方法暨介面與 記憶行為特性研究

Abstract

本研究主要探討陽極氧化氧化鋁與閘極絕緣層於碳化矽基板上的製程與應用。首先，研究分析了紫外光源照射對於陽極氧化的影響。結果顯示，在紫外燈照射下進行陽極氧化能夠促進碳化矽基板中電洞的產生，進而提升陽極氧化電流，並增強二氧化矽層的成長效率，此方法成功製備出厚度達16 奈米均勻的二氧化矽層。 本研究亦探討了間歇式噴霧水合氧化法及其改良版本── 重複噴霧式間歇水合氧化法在碳化矽基板上形成二氧化矽層的特性。結果顯示，重複噴霧式間歇水合氧化法可在950◦C 下形成厚度為3至6 奈米的均勻且緻密的二氧化矽薄膜，具有低漏電流的優勢。由電容-電壓特性，重複噴霧式間歇水合氧化法所成長的氧化層在碳化矽介面上的介面陷阱密度低至5×10^11 cm^−2 eV^−1。在不同紫外光強度下偏壓於-6 V，元件展現出線性的光響應特性，且可觀察到高達1300 的光暗電流比。 本研究亦將陽極氧化技術應用於在二氧化矽層上形成氧化鋁堆疊層，構築金屬/氧化鋁/二氧化矽/碳化矽金氧半結構。氧化鋁的製備方法包括熱蒸鍍後陽極氧化與原子層沉積。除了陽極氧化方法外，亦透過重複噴霧式間歇水合氧化法形成高品質的二氧化矽層。透過電流–電壓與電容–電壓等量測，比較不同製程條件下碳化矽基元件的電性特徵。實驗結果顯示，採用熱蒸鍍後陽極氧化製得的氧化鋁與重複噴霧式間歇水合氧化法製得的二氧化矽層，可實現介面陷阱密度低至2×10^11cm^−2eV^−1，具有較小的平帶電壓偏移與低漏電流特性。 最後，研究亦探討了閘極堆疊金氧半元件的記憶行為特性。實驗結果顯示，金屬/氧化鋁/(陽極氧化) 二氧化矽/碳化矽金氧半結構具有良好的記憶特性。在可靠度測試中，元件在100 次讀寫操作下可維持穩定的狀態0與狀態1電容。另外在暫態電流測試下，元件的暫態電流在1500次讀寫操作下，依舊可維持明顯的電流增益。並在寫入測試下，維持穩定電容間距達150秒。這些優異的成果展現碳化矽金氧半元件在記憶體領域的開發潛力。本研究亦輔以TCAD 模擬，以進一步分析電子濃度分佈、電場變化、電容–電壓特性曲線之漂移行為，以及暫態電流之響應特性，以全面探討元件在不同製程條件下之電性表現。

This paper primarily investigates the process and application of anodizing aluminum oxide (Al2O3) and gate insulation layers on silicon carbide-substrates. Initially,the study examines the influence of UVC illumination on the anodization process. It is found that anodization under UVC lamp (ANOUVC) facilitates more holes generation in the SiC substrate, thereby enhancing the anodization current and facilitating the growth of SiO2- layers. This method successfully grew SiO2 layers up to 16 nm thick with good uniformity. Furthermore, this research explores the characteristics of MIS devices with SiO2 formed by using Intermittent Spray Hydrated Oxidation (ISHO) and its- revised version of Intermittent Spray Hydrated Oxidation with Repetitive- Sprays (ISHO(r)). The results demonstrate that the ISHO(r) process can form uniform SiO2 with a thickness of 3∼ 6 nm, with low reverse leakage current. Interface characterization reveals that SiO2 grown by ISHO(r) has interface trap density (Dit) as low as 5×10^11 cm^−2eV^−1 at the SiO2/SiC interface. Under various UV light intensities at -6 V, the device exhibits linear responsivity with a photo-to-dark-current-ratio (PDCR) of 1300. The- anodization process is also applied to form Al2O3 stacking layers on the SiO2 layer, fabricating Al/Al2O3/SiO2/SiC(n) MOS structures. Two methods were used for Al2O3 formation, anodization after thermal- evaporation and atomic layer deposition (ALD). Besides the anodization process, Intermittent Spray Hydrated Oxidation with Repetitive Sprays is also used to form the SiO2 layer. I–V and C–V measurements were conducted to compare the electrical- characteristics of SiC devices under different process conditions. It is found that Al2O3 formed by "anodization after thermal evaporation" and SiO2 formed by ISHO(r), could produce interface trap density (Dit) as low as 2×10^11 cm^−2eV^−1 in addition to less flatband shift and low leakage. Finally, the memory characteristics of gate-stacking MOS devices were investigated. It is observed that Al/Al2O3/“ANO” SiO2/SiC(n) MOS structures exhibit good memory characteristics. In reliability tests, the device maintained stable capacitance for both state 0 and state 1 under 100 read/write operations. Furthermore, during transient current measurements, the device exhibited consistent current ratio even after 1500 read/write cycles. In the C–t retention test, a stable capacitance window was sustained for up to 150 seconds. These outstanding results demonstrate the potential of SiC-based MOS devices in memory applications. This study is further supported by TCAD simulations to analyze electron concentration distribution, electric field variation, the shift behavior of capacitance–voltage (C–V) characteristics, and transient current response. These analyses provide a comprehensive understanding of the device’s electrical performance under various process conditions.