考慮串擾效應之記憶體讀寫時序校準機制

Abstract

記憶體資料傳輸速率的不斷提升，高頻高速訊號所面臨的干擾問題越來越嚴重，尤以 Crosstalk（串擾）所造成的時序錯誤與符號邊界壓縮最為關鍵。傳統的記憶體訓練方法──Read/Write Centering──在進行 DQ 與 DQS 間的時序校準時，並未考慮鄰近訊號線的干擾，容易在實際操作中出現誤判，進而降低資料擷取的準確性與可靠性。 本研究提出一種「具 Crosstalk 感知能力的 Read/Write Centering 方法」，將最壞情境下的串擾影響納入訓練過程之中，透過分別執行 Speed-up 與 Slow-down Pattern 模擬，分析 BER（Bit Error Rate）分布並判斷可容許的 Timing Margin，進而推算出在 Crosstalk 條件下仍能穩定運作的最佳延遲設定值。為減少訓練時間，本研究亦導入群組化並行訓練的設計，有效降低訓練負擔。 本研究以 130 nm 製程、三條互連線構成的記憶體架構作為模擬平台，考慮不同的耦合電容值與三維時序偏移條件，總計模擬 1000 組隨機實例。結果顯示，與傳統 Read/Write Centering 相比，所提方法在 DQ2 通道上可提升 44.7% 的預測準確率，並有效減少 False Positive 與 False Negative 的發生，大幅提升整體校準的可信度與穩定性。由此可證明，所提方法不僅具備實務應用潛力，亦為未來高頻記憶體訓練流程提供一可擴展且具彈性的解決方案。

As modern memory systems continue to push data transfer speeds beyond multi-gigabit rates, signal integrity challenges such as crosstalk, skew, and timing jitter have become increasingly significant. Among these, crosstalk-induced distortions—particularly those that compress symbol widths or introduce asymmetric phase shifts—pose a serious threat to timing calibration accuracy. Conventional memory training techniques, such as Read/Write Centering, primarily focus on aligning data (DQ) and strobe (DQS) signals based on error-free regions, but typically overlook crosstalk interference from neighboring signals. In this thesis, we propose a Crosstalk-Aware Read/Write Centering method that actively incorporates worst-case crosstalk scenarios into the memory training process. The method leverages bit error rate (BER) profiling under both speed-up and slow-down crosstalk patterns to evaluate timing margin degradation, and subsequently identifies robust delay settings that ensure successful data sampling even under aggressive interference. A group-based calibration scheme is further introduced to accelerate training and reduce overall computational cost. The proposed approach is validated using a 130nm process model and a three-wire interconnect configuration, simulating over 1000 instances with varied skew and coupling capacitance values. Experimental results show a 44.7% improvement in prediction accuracy for DQ2 compared to conventional methods, and a significant reduction in false positive and false negative classifications. These findings confirm that the proposed method not only enhances the robustness of DDR timing calibration under crosstalk but also provides a scalable and flexible foundation for future high-speed memory interface designs.