Skip navigation

DSpace

機構典藏 DSpace 系統致力於保存各式數位資料(如:文字、圖片、PDF)並使其易於取用。

點此認識 DSpace
DSpace logo
English
中文
  • 瀏覽論文
    • 校院系所
    • 出版年
    • 作者
    • 標題
    • 關鍵字
    • 指導教授
  • 搜尋 TDR
  • 授權 Q&A
    • 我的頁面
    • 接受 E-mail 通知
    • 編輯個人資料
  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97341
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳中平zh_TW
dc.contributor.advisorChung-Ping Chenen
dc.contributor.author陳穎君zh_TW
dc.contributor.authorYing-Chun Chenen
dc.date.accessioned2025-05-07T16:05:58Z-
dc.date.available2025-09-03-
dc.date.copyright2025-05-07-
dc.date.issued2025-
dc.date.submitted2025-04-23-
dc.identifier.citation[1] S. P. Jeng and M. Liu, "Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)," 2022 International Electron Devices Meeting (IEDM), San Francisco, USA, pp. 3.2.1-3.2.4, 2022.
[2] Y. C. Hu, Y. M. Liang, H. P. Hu, C. Y. Tan, C. T. Shen, C. H. Lee and S. Y. Hou, "CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1022-1026, 2023.
[3] M. S. Lin, T. C. Huang, C. C. Tsai, K. H. Tam, K. C. H. Hsieh, C. F. Chen, W. H. Huang, C. W. Hu, Y. C. Chen, S. K. Goel, C. M. Fu, S. Rusu, C. C. Li, S. Y. Yang, M. Wong, S. C. Yang and F. Lee, "A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 956-966, 2020.
[4] P. K. Huang, C. Y. Lu, W. H. Wei, C. Chiu, K. C. Ting, C. Hu, C. H. Tsai, S. Y. Hou, W. C. Chiou, C. T. Wang, and D. Yu , "Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 101-104, 2021.
[5] W. C. Chen, C. Hu, K. C. Ting, V. Wei, T. H. Yu, S. Y. Huang, V. C. Y. Chang, C. T. Wang, S. Y. Hou, C. H. Wu and D. Yu, "Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology," in IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4071-4077, 2017.
[6] S. K. Goel, S. Adham, M. J. Wang, J. J. Chen, T. C. Huang, A. Mehta, F. Lee, V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, J. Cho, H. H. Lee, J. Choi and S. Kim, "Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study," 2013 IEEE International Test Conference (ITC), Anaheim, USA, pp. 1-10, 2013.
[7] P. Y. Lin, M. C. Yew, S. S. Yeh, S. M. Chen, C. H. Lin, C. S. Chen, C. C. Hsieh, Y. J. Lu, P. Y. Chuang, H. K. Cheng and S. P. Jeng, "Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 723-728, 2021.
[8] L. Lin, T. C. Yeh, J. L. Wu, G. Lu, T. F. Tsai, L. Chen and A. T. Xu, "Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology," 2013 IEEE 63rd Electronic Components and Technology Conference, Las Vegas, USA, pp. 366-371, 2013.
[9] C. F. Tseng, C. S. Liu, C. H. Wu and D. Yu, "InFO (Wafer Level Integrated Fan-Out) Technology," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 1-6, 2016.
[10] C. T. Wang and D. Yu, "Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 380-385, 2016.
[11] H. P. Pu, H. J. Kuo, C. S. Liu and D. C. H. Yu, "A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO Packaging," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 45-51, 2018.
[12] T. Ko, H. P. Pu, Y. Chiang, H. J. Kuo, C. T. Wang, C. S. Liu and D. C. H. Yu, "Applications and Reliability Study of InFO_UHD (Ultra-High-Density) Technology," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1120-1125, 2020.
[13] S. R. Chun, T. H. Kuo, H. Y. Tsai, C. S. Liu, C. T. Wang, J. S. Hsieh, T. S. Lin, T. Ku and D. Yu, "InFO_SoW (System-on-Wafer) for High Performance Computing," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1-6, 2020.
[14] Y. P. Chiang, S. P. Tai, W. C. Wu, J. Yeh, C. T. Wang and D. C. H. Yu, "InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 130-135, 2021.
[15] C. T. Wang, T. C. Tang, C. W. Lin, C. W. Hsu, J. S. Hsieh, C. H. Tsai, K. C. Wu, H. P. Pu and D. Yu, "InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 202-207, 2018.
[16] C. W. Hsu, C. H. Tsai, J. S. Hsieh, K. C. Yee, C. T. Wang and D. Yu, "High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL," 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 254-259, 2017.
[17] C. T. Wang and D. Yu, "Power-Performance Advantages of InFO Technology for Advanced System Integration," 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, pp. 1-4, 2019.
[18] C. H. Hsu, Y. J. Lin, S. L. Kuo, Y. H. Peng, C. W. Pan, T. Y. Chen and W. S. Hsu, "Thermal Characteristics of Integrated Fan-Out on Substrate (InFO_oS) Packaging Technology," 2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, USA, pp. 212-218, 2020.
[19] C. C. Hu, M. F. Chen, W. C. Chiou and D. C. H. Yu, "3D Multi-chip Integration with System on Integrated Chips (SoIC™)," 2019 Symposium on VLSI Technology, Kyoto, Japan, pp. T20-T21, 2019.
[20] S. W. Liang, G. C. Y. Wu, K. C. Yee, C. T. Wang, J. J. Cui and D. C. H. Yu, "High Performance and Energy Efficient Computing with Advanced SoIC™ Scaling," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 1090-1094, 2022.
[21] C. H. Tsai, T. Ku, M. F. Chen, W. C. Chiou, C. T. Wang and D. Yu, "Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)," 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, pp. 1-2, 2020.
[22] M. F. Chen, C. S. Lin, E. B. Liao, W. C. Chiou, C. C. Kuo, C. C. Hu, C. H. Tsai, C. T. Wang and D. Yu, "SoIC for Low-Temperature, Multi-Layer 3D Memory Integration," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 855-860, 2020.
[23] D. C. H. Yu, C. T. Wang, C. C. Lin, C. H. Lu, G. Wu, C. Y. Huang, W. T. Chen, T. Ku, K. C. Yee and C. H. Tsai, "SoIC_H Technology for Heterogeneous System Integration," in IEEE Transactions on Electron Devices, vol. 69, no. 12, pp. 7167-7172, 2022.
[24] M. F. Chen, F. C. Chen, W. C. Chiou and D. C. H. Yu, "System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 594-599, 2019.
[25] H. J. Chia, S. P. Tai, J. J. Cui, C. T. Wang, C. H. Tung, K. C. Yee and D. C. H. Yu, "Ultra High Density Low Temperature SoIC with Sub-0.5 μm Bond Pitch," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1-4, 2023.
[26] Y. H. Chen, C. A. Yang, C. C. Kuo, M. F. Chen, C. H. Tung, W. C. Chiou and D. Yu, "Ultra High Density SoIC with Sub-micron Bond Pitch," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 576-581, 2020.
[27] F. Xie, R. Chen and T. Wei, "Thermal Mitigation Strategy for Backside Power Delivery Network," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, USA, pp. 1485-1492, 2024.
[28] R. Chen, G. Sisto, M. Stucchi, A. Jourdain, K. Miyaguchi, P. Schuddinck, P. Woeltgens, H. Lin, N. Kakarla, A. Veloso, D. Milojevic, O. Zografos, P. Weckx, G. Hellings, G. Van Der Plas, J. Ryckaert and E. Beyne, "Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, USA, pp. 429-430, 2022.
[29] A. Veloso, B. Vermeersch, R. Chen, P. Matagne, M. G. Bardon, G. Eneman, K. Serbulova, O. Zografos, S. H. Chen, G. Sisto, A. Jourdain, H. Arimura, B. O’Sullivan, A. De Keersgieter, G. Hellings, E. Beyne, N. Horiguchi and J. Ryckaert, "Backside Power Delivery: Game Changer and Key Enabler of Advanced Logic Scaling and New STCO Opportunities," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 1-4, 2023.
[30] J. Lee, J. Jeong, S. Lee, S. Lee, J. Lim, S. C. Song, S. Ekbote, N. Stevens Yu, D. Greenlaw and R. H. Baek, "Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, pp. 1-2, 2023.
[31] W. Hafez et al., "Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, pp. 1-2, 2023.
[32] S. S. T. Nibhanupudi, S. Oruganti, R. Mathur, N. Gupta, M. Wang and J. P. Kulkarni, "Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges," 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA, 2023, pp. 1-4, 2023.
[33] H. Oprins, J. L. Ramirez Bohorquez, B. Vermeersch, G. Van der Plas and E. Beyne, "Package level thermal analysis of backside power delivery network (BS-PDN) configurations," 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm), San Diego, USA, pp. 1-7, 2022.
[34] R. Chen, M. Lofrano, G. Mirabelli, G. Sisto, S. Yang, A. Jourdain, F. Schleicher, A. Veloso, O. Zografos, P. Weckx, G. Hiblot, G. V. d. Plas, G. Hellings, J. Ryckaert and E. Beyne, "Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network," 2022 International Electron Devices Meeting (IEDM), San Francisco, USA, pp. 23.4.1-23.4.4, 2022.
[35] M. Kobrinsky et al., "Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking," 2023 International Electron Devices Meeting (IEDM), San Francisco, USA, pp. 1-4, 2023.
[36] S. Kim, G. M. Kim, S. N. Kim, S. Ahn, Y. S. Kim, I. Jang, K. W. Lee and D. S. Kim, "Structural Reliability and Performance Analysis of Backside PDN," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, pp. 1-2, 2023.
[37] Y. L. Shen, "Analysis of Joule heating in multilevel interconnects," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, , vol. 17, pp. 2115-2121, 1999.
[38] K. W. Yan, P. Y. Lin and S. L. Kuo, "Thermal Challenges for HPC 3DFabricTM Packages and Systems," 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, pp. 4C.1-1-4C.1-6, 2022.
[39] K. Yan, P. Y. Lin and S. L. Kuo, "Thermal Challenges for HPC 3DIC Packages and Systems," 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Oita, Japan, pp. 151-153, 2022.
[40] B. Bai, S. Chen, W. Wang, H. Hao and L. Li, "Thermal management of integrated circuits in burn-in environment," The Proceedings of 2011 9th International Conference on Reliability, Maintainability and Safety, Guiyang, China, pp. 1092-1095, 2011.
[41] S. Shi, X. Zhang and R. Luo, "The thermal-aware floorplanning for 3D ICs using Carbon Nanotube," 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 1155-1158, 2010.
[42] A. L. Moore and Li Shi, "Emerging challenges and materials for thermal management of electronics," Materials Today, vol. 17, pp. 163-174, 2014.
[43] S. P. Gurrum, S. K. Suman, Y. K. Joshi and A. G. Fedorov, "Thermal issues in next-generation integrated circuits," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 4, pp. 709-714, 2004.
[44] F. Tavakkoli, S. Ebrahimi, S. Wang, K. Vafai, "Analysis of critical thermal issues in 3D integrated circuits," International Journal of Heat and Mass Transfer, vol. 97, pp. 337-352, 2016.
[45] Peng Li, L. T. Pileggi, M. Asheghi and R. Chandra, "Efficient full-chip thermal modeling and analysis," IEEE/ACM International Conference on Computer Aided Design, 2004. (ICCAD), San Jose, USA, pp. 319-326, 2004.
[46] M. Pedram and S. Nazarian, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods," Proceedings of the IEEE, vol. 94, no. 8, pp. 1487-1501, 2006.
[47] A. Jain, R. E. Jones, Ritwik Chatterjee, S. Pozder and Zhihong Huang, "Thermal modeling and design of 3D integrated circuits," 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Orlando, USA, pp. 1139-1145, 2008.
[48] Sungjun Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," International Electron Devices Meeting 2000. Technical Digest. (IEDM), San Francisco, USA, pp. 727-730, 2000.
[49] Z. Cao, J. Li, J. Tao and Y. Chen, "3D Compact Thermal Model and its Application on Fast Chip Level Thermal Simulation," 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, pp. 246-249, 2023.
[50] A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler and D. Atienza, "3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling," 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 463-470, 2010.
[51] M. N. Ozisik, "Finite Difference Methods in Heat Transfer," New York:CRC, 1994.
[52] Wei Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron and M. R. Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 501-513, 2006.
[53] T. Y. Wang and Charlie C. P. Chen, "3-D Thermal-ADI: a linear-time chip level transient thermal simulator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ICCAD), vol. 21, no. 12, pp. 1434-1445, 2002.
[54] J. Li, M. Tang and J. Mao, "An Efficient ADI Method for Transient Thermal Simulation of Liquid-Cooled 3-D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 9, pp. 1484-1491, 2022.
[55] R. W. Lewis, P. Nithiarasu, K. N. Seetharamu, "Fundamentals of the Finite Element Method for Heat and Fluid Flow," Wiley, 2004.
[56] B. Li, M. Tang, Y. Zhi and H. Yu, "Thermal Simulation of 3-D Stacked Integrated Circuits with Layered Finite Element Method," 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall), Xiamen, China, pp. 1883-1886, 2019.
[57] B. Li, M. Tang, P. Li and J. Mao, "Efficient Thermal Analysis of Integrated Circuits and Packages With Microchannel Cooling Using Laguerre-Based Layered Finite Element Method," IEEE Journal on Multiscale and Multiphysics Computational Techniques, vol. 8, pp. 195-204, 2023.
[58] D. Oh, C. C. P. Chen and Y. H. Hu, "Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 11, pp. 1767-1771, 2012.
[59] L. Codecasa, V. d'Alessandro, A. Magnani, N. Rinaldi and P. J. Zampardi, "Fast novel thermal analysis simulation tool for integrated circuits (FANTASTIC)," 20th International Workshop on Thermal Investigations of ICs and Systems, Greenwich, UK, 2014, pp. 1-6.
[60] Ansys, "Ansys Collaborates with TSMC to Deliver Thermal Analysis Solution for 3D IC Designs," https://www.ansys.com/en-in/news-center/press-releases/10-27-21-ansys-collaborates-with-tsmc-to-deliver-thermal-analysis-solution-for-3d-ic-designs, 2021.
[61] M. Roshandell, "Successful Thermal Management of 3D-ICs: Accurate, Fast, Efficient and Scalable with Celsius," https://community.cadence.com/cadence_blogs_8/b/pcb/posts/successful-thermal-management-of-3d_2d00_ics, 2022.
[62] Z. Tokei, H. Oprins, M. Lofrano, and X. Chang, "Mitigating the thermal bottleneck in advanced interconnects," Chip Scale Review, vol. 27, pp. 43-48, 2023.
[63] B. Allard, X. Jorda, P. Bidan, A. Rumeau, H. Morel, X. Perpina, M. Vellvehi and S. M'Rad, "Reduced-Order Thermal Behavioral Model Based on Diffusive Representation," in IEEE Transactions on Power Electronics, vol. 24, no. 12, pp. 2833-2846, 2009.
[64] X. Dong, A. Griffo, D. Hewitt and J. Wang, "Reduced-Order Thermal Observer for Power Modules Temperature Estimation," in IEEE Transactions on Industrial Electronics, vol. 67, no. 12, pp. 10085-10094, 2020,.
[65] A. Quarteroni, A. Valli, "Domain Decomposition Methods for Partial Differential Equations," Oxford University Press, 1999.
[66] A. Toselli, Olof B. Widlund, "Domain Decomposition Methods - Algorithms and Theory," Springer, 2004.
[67] W. Yu, T. Zhang, X. Yuan and H. Qian, "Fast 3-D Thermal Simulation for Integrated Circuits With Domain Decomposition Method," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 12, pp. 2014-2018, 2013.
[68] N. Liu, C. Wang, C. Xi, Q. Wu, Q. Liu, M. Zhuang, L. Shi and Q. H. Liu, "The Domain Decomposition Method With Adaptive Time Step for the Transient Thermal Analysis of 3-D ICs," in IEEE Access, vol. 11, pp. 48069-48079, 2023.
[69] X. Zhang and M. Tang, "Non-Conformal Domain Decomposition Method for Thermal Analysis of Integrated Packages," 2022 IEEE 10th Asia-Pacific Conference on Antennas and Propagation (APCAP), Xiamen, China, pp. 1-2, 2022.
[70] J. Xie and M. Swaminathan, "System-Level Thermal Modeling Using Nonconformal Domain Decomposition and Model-Order Reduction," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 1, pp. 66-76, 2014.
[71] B. Barabadi, S. Kumar, V. Sukharev, Y. K. Joshi, "Multiscale Transient Thermal Analysis of Microelectronics." Journal of Electronic Packaging, vol. 137, 2015.
[72] L. Tang, Y. K. Joshi, "A Multi-Grid Based Multi-Scale Thermal Analysis Approach for Combined Mixed Convection, Conduction, and Radiation Due to Discrete Heating," ASME Journal of Heat and Mass Transfer, vol. 127, 2005.
[73] M. Reuter, S. Biasotti, D. Giorgi, G. Patanè, and M, Spagnuolo. "Discrete Laplace–Beltrami operators for shape analysis and segmentation, " Computers & Graphics, vol. 33, pp. 381-390, 2009.
[74] O'Reilly, Randall C., and Jeffrey M. Beck. "A family of large stencil discrete Laplacian approximations in three dimensions, " International Journal for Numerical Methods in Engineering, pp. 1-16, 2006.
[75] K. D. Cole, M. R. Yavari, and P. K. Rao, "Computational heat transfer with spectral graph theory: Quantitative verification, " International Journal of Thermal Sciences, vol. 153, 106383, 2020.
[76] S. K. Jeng, "Finite Element Method 2D: Rectangle Bases," Unpublished internal presentation, 2024.
[77] KC, G., & Dulal, R. P., "Adaptive Finite Element Method for Solving Poisson Partial Differential Equation," Journal of Nepal Mathematical Society, vol. 4, no. 1, pp. 1–18, 2021.
[78] S. K. Jeng, " Boundary Condition Errors and Profiling," Unpublished internal presentation, 2024.
-
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97341-
dc.description.abstract本論文針對現代超大規模積體電路(VLSI)設計中所面臨的熱模擬挑戰提出了一套解決方案。隨著積體電路在結構複雜度與功率密度上的不斷提升,傳統熱分析方法因記憶體需求過大與運算時間過長而變得效率低下。為克服此一瓶頸,本研究引入基於域分解與多尺度技術的新穎框架,將整體熱問題拆分為數個可獨立計算的子域分別計算,降低峰值記憶體用量。模擬結果顯示,與傳統有限元素分析相比,所提出之求解器在記憶體使用量上可減少 7.79 倍,同時在誤差極小的前提下維持高準確度。此外,運算效能的顯著提升,亦使得包含數百萬元素之IC封裝模擬成為可能。
本論文另一項核心貢獻在於構建了一個具高度彈性的元方法(meta-method)框架,容許以不同方法替換核心有限元素求解器,例如整合商用電子設計自動化(EDA)工具或基於機器學習的偏微分方程求解器,以進一步提升整體效能。本論文的多樣化策略不僅加速了迭代求解過程的收斂,亦為未來整合更多物理現象(如電行為與機械應力)於多物理場模擬中奠定了堅實基礎。
zh_TW
dc.description.abstractThis thesis presents a solution to the thermal simulation challenges inherent in modern VLSI design. As integrated circuits grow in complexity and power density, traditional thermal analysis methods become inefficient due to excessive memory requirements and prolonged runtimes. To overcome these limitations, this work introduces a novel framework based on domain decomposition and multiscale techniques that partitions the global thermal problem into manageable subdomains. Simulation results demonstrate that the proposed solver achieves a 7.79× reduction in memory usage compared to conventional finite element analysis, while maintaining high accuracy with minimal error. In addition, significant improvements in runtime performance enable efficient simulation of IC packages comprising millions of elements.
A key contribution of this thesis is the development of a flexible, meta-method framework that supports the replacement of the core finite element solver with alternative approaches, such as commercial EDA tools or machine learning–based PDE solvers, to further enhance performance. This versatility not only accelerates the convergence of the iterative solution process but also opens the door to integrating additional physical phenomena, such as electrical behavior and mechanical stress, in future multiphysics simulations.
en
dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-05-07T16:05:58Z
No. of bitstreams: 0
en
dc.description.provenanceMade available in DSpace on 2025-05-07T16:05:58Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontents致謝 A
中文摘要 C
ABSTRACT I
LIST OF CONTENTS III
LIST OF FIGURES VIII
LIST OF TABLES XII
LIST OF SYMBOLS XIII
LIST OF ABBREVIATIONS XVII
CHAPTER 1 INTRODUCTION 1
1.1 Background and Motivation 1
1.2 Literature Review 2
1.2.1 Advanced Packaging and Chip Stacking Techniques 2
1.2.2 Back-Side Power Delivery Network (BSPDN) 5
1.2.3 Thermal Issue in the 2D and 3D IC 6
1.2.4 Thermal Modeling and Simulation Techniques 6
1.2.5 Domain Decomposition Method and Multiscale Technique 8
1.3 Structure of the Thesis 9
CHAPTER 2 OVERVIEW OF THERMAL SIMULATION IN IC DESIGN 11
2.1 Chapter Introduction 11
2.2 Thermal Simulation Flow for Integrated Circuit 11
2.2.1 Data Requirements 12
2.2.2 Power and IR Analysis 12
2.2.3 Building Thermal Model and Mesh Generation 12
2.2.4 Obtaining Temperature Profile 13
2.3 Modeling Strategy 14
2.3.1 The Scale of Thermal Simulation for Integrated Circuit 14
2.3.2 Tile-Based Thermal Model 16
2.4 Overview of Heat Transfer Equations 17
2.4.1 Energy Balance on a Differential Control Volume 17
2.4.2 Incorporating Fourier’s Law 18
2.4.3 Boundary Conditions 18
CHAPTER 3 FINITE ELEMENT METHOD FOR SOLVING HEAT TRANSFER EQUATIONS 21
3.1 Chapter Introduction 21
3.2 Overview of The Finite Element Method 21
3.2.1 Discretization 21
3.2.2 Formulation 23
3.2.3 Assemble the Element Equations 25
3.2.4 Solve the System of Equations 26
3.3 Steady State Heat Transfer in Two Dimension 27
3.3.1 Weak Formulation 27
3.3.2 Finite Element Discretization 27
3.3.3 Boundary Condition Assessment 30
CHAPTER 4 THERMAL SOLVER IMPLEMENTATION WITH PROPOSED MULTISCALE DOMAIN DECOMPOSITION METHOD 32
4.1 Chapter Introduction 32
4.2 Introduction to Domain Decomposition Method 32
4.2.1 Problem Definition in Matrix and Vector Form 32
4.2.2 Schur Complement System 33
4.3 Neumann-Neumann Algorithm 34
4.3.1 Definition and Matrix Form of the Algorithm 34
4.3.2 Introduction to Richardson Iteration 35
4.3.3 Interface Correction 36
4.3.4 Convergence Analysis 38
4.3.5 Algorithm for Steady-State Heat Transfer Analysis 42
4.4 Multiscale Technique 50
4.4.1 Fundamental Concept 50
4.4.2 Error Reduction Analysis 51
4.5 Program Implementation 53
4.5.1 Finite Element Analysis Solver 53
4.5.2 Model Generation 54
4.5.3 Multiscale Preprocess 57
4.5.4 Domain Decomposition Solver 59
CHAPTER 5 SIMULATION RESULT AND VALIDATION 62
5.1 Chapter Introduction 62
5.2 Simulation Setup 62
5.2.1 Model Configuration 62
5.2.2 Computational Environment 72
5.3 Simulation Result 72
5.3.1 Temperature Distribution and Error Analysis 72
5.3.2 Runtime and Iteration Analysis 88
5.3.3 Memory Usage Analysis 93
CHAPTER 6 CONCLUSIONS 96
REFERENCES 98
A. CoWoS 98
B. InFO 100
C. SoIC 102
D. BSPDN 104
E. Thermal Issue 106
F. Thermal Modeling and Simulation Techniques 107
G. DDM and Multiscale 111
H. Discrete Laplace operator 112
I. Finite Element Method Implementation 113
-
dc.language.isoen-
dc.subject有限元素法zh_TW
dc.subject域分解法zh_TW
dc.subject數值方法zh_TW
dc.subject熱分析zh_TW
dc.subject三維積體電路zh_TW
dc.subject先進封裝zh_TW
dc.subjectDomain Decomposition Methoden
dc.subjectFinite Element Methoden
dc.subjectAdvanced Packagingen
dc.subject3DICen
dc.subjectThermal Analysisen
dc.subjectNumerical Analysisen
dc.title基於多尺度技術的穩態熱分析域分解方法zh_TW
dc.titleDomain Decomposition Method for Steady-State Thermal Analysis with Multiscale Techniqueen
dc.typeThesis-
dc.date.schoolyear113-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee鄭士康;陳偉倫;張簡維平zh_TW
dc.contributor.oralexamcommitteeShyh-Kang Jeng;Woei-Luen Chen;Wei-Pin Changchienen
dc.subject.keyword有限元素法,域分解法,數值方法,熱分析,三維積體電路,先進封裝,zh_TW
dc.subject.keywordFinite Element Method,Domain Decomposition Method,Numerical Analysis,Thermal Analysis,3DIC,Advanced Packaging,en
dc.relation.page113-
dc.identifier.doi10.6342/NTU202500854-
dc.rights.note未授權-
dc.date.accepted2025-04-24-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
dc.date.embargo-liftN/A-
顯示於系所單位:電子工程學研究所

文件中的檔案:
檔案 大小格式 
ntu-113-2.pdf
  未授權公開取用
17.59 MBAdobe PDF
顯示文件簡單紀錄


系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。

社群連結
聯絡資訊
10617臺北市大安區羅斯福路四段1號
No.1 Sec.4, Roosevelt Rd., Taipei, Taiwan, R.O.C. 106
Tel: (02)33662353
Email: ntuetds@ntu.edu.tw
意見箱
相關連結
館藏目錄
國內圖書館整合查詢 MetaCat
臺大學術典藏 NTU Scholars
臺大圖書館數位典藏館
本站聲明
© NTU Library All Rights Reserved