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  1. NTU Theses and Dissertations Repository
  2. 重點科技研究學院
  3. 積體電路設計與自動化學位學程
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97302
Title: 使用SOMAC預測多核處理器的最小工作電壓以及最差核的最小工作電壓
Multi core Vmin and Worst core Vmin prediction using SOMAC
Authors: 廖政毓
Jeng-Yu Liao
Advisor: 李建模
Chien-Mo Li
Keyword: 晶片效能預測,非破壞性壓力測試,
Chip performance prediction,Nondestructive stress test,
Publication Year : 2025
Degree: 碩士
Abstract: 我們提出了一種全面的流程,用於透過壓力測試識別高的最小工作電壓晶片並預測最小工作電壓。該方法透過處理壓力測試失敗記錄檔生成名為CSCP的特徵,旨在應對新的測試架構所帶來的挑戰。為了提高預測準確性,我們採用了結合Pearson 相關係數和F回歸的雙階段特徵選擇方法。此外,我們使用遺傳算法來選擇與最小工作電壓相關的特定測試圖樣,大幅縮短測試時間。為了考慮Vmin在多核CPU中的差異,我們應用了多核Vmin模型(多模型)來預測每個核心的Vmin,並應用了單個最差核心Vmin模型(單模型)來預測最差核心的Vmin。
在先進的4nm多核CPU設計上的實驗結果表明,所提出的兩階段方法有效地選擇了不同核心中的重要特徵。此外,我們的方法在高的最小工作電壓晶片識別中實現了超過93%的測試圖樣減少率,在最小工作電壓預測中實現了超過66%的測試圖樣減少率。使測試時間比傳統方法加快了80倍以上。此外,各核最小工作電壓的均方根誤差低至8.30mV,而最差核最小工作電壓的均方根誤差低至7.07 mV 。對於每個核心Vmin預測(使用多模型),平均RMSE低至8.30mV,與單模型相比減少了30%的誤差。同樣,對於最差核心Vmin預測(使用單模型),RMSE低至7.07mV,與多模型相比減少了7.59%的誤差。
We propose a comprehensive method for identifying high Vmin chips and predicting Vmin through stress test. Our approach processes stress-test fail-logs to generate features, known as CSCP, designed to address the challenges of the new scan compression structure. To enhance prediction accuracy, we select important features using a two-phase approach that combines Pearson correlation and F-regression. Additionally, we employ genetic algorithms to select specific test patterns correlated with Vmin, significantly reducing test time. To account for the variation in Vmin across CPU cores, we apply multi-core Vmin model (multi-model) to predict each-core Vmin and apply single worst-core Vmin model (single-model) to predict the worst-core Vmin.
Experimental results on advanced 4nm multi-core CPU designs demonstrate that the proposed two-phase approach effectively select important features across different cores. Our approach achieves over 93% reduction in test patterns for high Vmin chips identification and over 66% reduction in test patterns for Vmin prediction. This approach can save test time by more than 80 times compared to traditional Vmin measurement methods. For each-core Vmin prediction using multi-model, the average RMSE is as low as 8.30 mV, achieving a 30% error reduction compared to the single-model. Similarly, for worst-core Vmin prediction using single-model, the RMSE is as low as 7.07 mV, offering a 7.59% error reduction compared to the multi-model.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97302
DOI: 10.6342/NTU202500553
Fulltext Rights: 未授權
metadata.dc.date.embargo-lift: N/A
Appears in Collections:積體電路設計與自動化學位學程

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