低溫磁控濺鍍製備之P型碲/氧化碲薄膜電晶體之研究

Abstract

碲為元素週期表第16族(VI A族)第五週期之元素，原子序為52，屬於類金屬，其元素或氧化而成的氧化碲，費米能階靠近價代，屬於P型半導體的特性。但是碲作為通道層時，載子傳遞容易受其其內部的結晶情形影響。碲薄膜結晶時，容易因成長晶粒過小以及成核點(nucleation)的不易控制，導致碲薄膜呈現隨機取向的多晶六角晶相結構，因多晶六角晶相而增加的晶界(grain boundary)會導致載子受到陷阱捕捉的情況增加，進而阻礙載子的傳輸，導致其關電流過高，元件電流開關特性不理想，提升其結晶性為研究者努力的目標。 本論文研究碲薄膜電晶體製程為下閘極交錯型結構，將依序探討不同工作壓力下對不同鍍膜時間之厚度，確認最佳厚度參數後，利用提高在濺鍍過程中的氧氣分量使通道層氧化成非晶相的氧化碲薄膜。機制為提升通道層的氧化程度來降低碲在不同成長軸向(c軸)之結晶速度，抑制晶粒的成長。氧化碲薄膜中的Te 5p軌域可以緩解由O 2p軌域帶來的侷限(localized)使關電流降低。後續藉由改變絕緣層來探討絕緣層介面對於碲薄膜電晶體的開關特性影響。藉由沉積氧化鋁鈍化層，使通道層中氧化碲的氧擴散進入鈍化層中，透過降低由氧化過程所產生的介面能來提升碲的結晶性，減緩費米能階被固定的情形，使通道層更容易產生空乏，也從XRD印證這件事。再透過不同絕緣層封裝後之特徵參數比較，找出最佳表現的碲薄膜應為能夠在維持開電流的同時，關電流有明顯下降，且臨界電壓為最小的結果，發現最佳表現的碲薄膜電晶體電性在VDS = -1 V時，氧化鋁鈍化層處理之絕緣層為150度 HfO2、250度 HfO2和150度 Al2O3氧化碲薄膜電晶體，電流開關比分別為〖1.97×10〗^3、 〖7.90×10〗^2和〖1.28×10〗^3，臨界電壓分別為1.02 V、2.79 V和0.06V，場效載子遷移率分別為1.02 cm^2 V^(-1) s^(-1)、0.674 cm^2 V^(-1) s^(-1)和0.867 cm^2 V^(-1) s^(-1)，次臨界擺幅分別為3.58 V/dec、4.04 V/dec和3.49 V/dec。結果顯示以氧化鋁作為絕緣層可以最有效使臨界電壓左移，且〖∆V〗_TH最小，最後在長時間偏壓量測中，發現沉積鈍化層之元件受長時間正或負偏壓後載子回復之情形非常快速。

Tellurium (Te) is an element in Group 16 (Group VI A) and the fifth period of the periodic table, with an atomic number of 52. It is classified as a metalloid. Tellurium and its oxidized form, tellurium oxide (TeOx), exhibit p-type semiconductor characteristics due to the Fermi level being close to the valence band. However, when Te is used as a channel layer, carrier transport is easily affected by the internal crystalline conditions. During Te thin film crystallization, issues often arise due to the rapid and uncontrollable nucleation of Te films during deposition, resulting in the formation of small grains with random orientation polycrystalline hexagonal phase structure. The increased grain boundaries resulting from the polycrystalline hexagonal phase cause more carrier trapping, hindering carrier transport and resulting in high off-current and bad current switching characteristics of the device. Enhancing the crystallinity has become a focus for researchers. The Te thin-film transistors (TFTs) developed in this thesis have a bottom-gate staggered structure. The effects of channel thickness, working pressures, oxygen flow rate and gate dielectric are systematically investigated. The channel layer is oxidized into an amorphous TeOx film by increasing the oxygen content during the sputtering process. The mechanism involves enhancing the oxidation degree of the channel layer to reduce the crystallinity of Te along different growth axes (c-axis), thereby suppressing grain growth. It is because, in the TeOx film, the Te 5p orbital mitigates the localization effect caused by the O 2p orbital, which lowers the off-state current. By depositing an aluminum oxide passivation layer, the diffusion of oxygen from the TeOx channel layer into the passivation layer reduces the interfacial energy generated during the oxidation process. This enhances the crystallinity of tellurium, alleviates Fermi level pinning, and facilitates channel depletion. Comparing the characteristic parameters of devices with different dielectric layers, the best-performing Te TFTs simultaneously maintain high on-state current, exhibit significantly reduced off-state current, and achieve minimal threshold voltage. The best-performing aluminum oxide passivated Te TFTs with insulators of 150°C HfO₂, 250°C HfO₂, and 150°C Al₂O₃ exhibited current on-off current ratios of 1.97×10³, 7.90×10², and 1.28×10³, threshold voltages of 1.02 V, 2.79 V, and 0.06 V, field-effect mobilities of 1.02 cm² V⁻¹ s⁻¹, 0.674 cm² V⁻¹ s⁻¹, and 0.867 cm² V⁻¹ s⁻¹, and subthreshold swings of 3.58 V/dec, 4.04 V/dec, and 3.49 V/dec, respectively. The result reveals that using aluminum oxide as the dielectric layer effectively shifts the threshold voltage to the left, with the smallest ΔVTH. Finally, during long-term bias stress measurements, it is observed that devices with passivation layers exhibit rapid recovery after prolonged positive or negative bias stresses.