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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96386| Title: | 於現場可程式化邏輯閘陣列實作後量子密碼系統關鍵元件 On the FPGA Implementation of Polynomial Multiplications and Fast Modulo Reduction Operations in Post-Quantum Cryptosystems |
| Authors: | 彭柏源 Bo-Yuan Peng |
| Advisor: | 陳和麟 Ho-Lin Chen |
| Keyword: | 現場可程式化邏輯閘陣列,多項式乘法,數論轉換,古德法,取模運算,迪傑比編碼, FPGA,Polynomial Multiplication,NTT,Good's Trick,Modulo Reduction,DJB Codec, |
| Publication Year : | 2025 |
| Degree: | 博士 |
| Abstract: | 後量子密碼學 (尤以格基密碼學為甚) 的計算過程經常需要快速的多項式乘法與取模運算,另外各種後量子密碼系統的向量值域範圍經常不是二的次方數,以致各種向量直接儲存傳遞時無法有效利用所有位元的消息含量。作者提出於現場可程式化邏輯閘陣列實作基於數論轉換的多項式乘法元件的暫存器傳輸級硬體之描述程式生成系統,可以自由生成基於全點型、古德三型或古德五型數論轉換的多項式乘法元件;應對各種不同模數與輸入位元數的高速取模運算元件的暫存器傳輸及硬體之描述程式生成系統;應對各種不同向量值域範圍的迪傑比編碼器,以達成各種相關運算的硬體加速。 On the Post-Quantum Cryptography, especially the Lattice-Based Cryptography, fast polynomial multiplications with fast modulo operations are necessary. Also, the range of the entries of various vectors in PQC is not necessarily the power of 2, which makes the bits saving data or being transported not information effective. The author proposed the RTL generators of polynomial multiplication with various configurations based on the implementation of the full-point NTT and/or the Good's Trick NTT (with factor 3 or 5); the RTL generators of fast arbitrary modulo operation with arbitrary input bits; the RTL implementation of DJB Codec with parameter generator, generating arbitrary configuration fitting the requirement. These designs provide the hardware acceleration of the above computation requirements for PQC. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96386 |
| DOI: | 10.6342/NTU202500332 |
| Fulltext Rights: | 同意授權(全球公開) |
| metadata.dc.date.embargo-lift: | 2025-02-14 |
| Appears in Collections: | 電機工程學系 |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-113-1.pdf | 1.63 MB | Adobe PDF | View/Open |
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