應用於VLSI電源傳輸網絡之階級式多執行緒靜態電壓模擬

Abstract

在先進製程的持續發展下，由於電壓持續下降，帶寬需求又持續上升，電路實體設計的演算法較以往更為困難。因此，設計電源供應網絡（PDN）需要充分考慮線寬比、電壓降甚至是熱效應等多個方面，確保電路在穩定的工作電壓上。 本文著重於開發基於節點分析法的階層式電壓降模擬器，並結合多執行緒平行處理的矩陣解算器。在IBMPG基準上，一般方法速度相較於黃金工具 Synopsys HSPICE 達到了 10 倍的提升，並將準確性損失控制在10-6伏特。在預先切割好的自製基準中，階層式方法跟一般方法比較速度快了32%。而在預先切割好的且有部分重複子電路的自製基準中，階層式方法跟一般方法比較速度快了118%。

With the continuous advancement in advanced processes, the decreasing voltage and increasing bandwidth demands make circuit physical design algorithms more challenging than before. Therefore, designing the power delivery network (PDN) requires thorough consideration of various aspects such as line width ratio, voltage drop, and even thermal effects to ensure that the circuit operates at a stable working voltage. This paper focuses on developing a hierarchical voltage drop simulator based on the nodal analysis method combined with a multi-thread matrix solver. On the IBM benchmark, the speed achieved is 10 times faster than the golden tool Synopsys HSPICE, with at most 10−6V accuracy loss. The hierarchical method is 32% faster than the general method in the pre-cut homemade benchmarks. In the pre-cut homemade benchmarks with duplicated subcircuits, the hierarchical method is 118% faster than the general method.