應用於V頻段低相位變異之可變增益低雜訊放大器、高線性度降頻器及D頻段次諧波正交升頻器之設計

Abstract

本篇論文包含以下三個部分：V頻段低相位變異低雜訊可變增益放大器，V頻段高線性度降頻器，以及D頻段次諧波正交升頻器的量測與模擬結果。 第一個部分將會著重於V-band低相位變異低雜訊可變增益放大器的設計。此低雜訊可變增益放大器主要應用在V頻段的相位陣列系統中。此研究使用90奈米互補式金氧化物半導體電晶體製程來製作。為了實現低相位變異，該電路採用了電感性的相位反轉網路，以反轉電流控制(current-steering)架構的輸出相對控制電壓的相位變化趨勢。這使得兩級串接的電流控制架構之可變增益放大器具有相位相互抵消的效果，從而實現低相位變異的特性。此外，輸入端使用了雙重變壓器耦合（double-transformer-coupling）的技術，以提高整體電路的增益和穩定性，同時降低雜訊指數和直流功耗。此可變增益低雜訊放大器的量測結果為：最高增益20.7 dB，3 dB頻寬為55-62 GHz，最低雜訊指數5.3 dB，3 dB頻寬內的相對相位偏移為6.3度，均方根相位誤差為2.45度。 第二個部分聚焦於V頻段高線性度降頻器的設計，主要應用於高線性度接收機或解調系統中。此研究同樣使用90互補式金氧化物半導體製程來製作。為了提升混頻器的整體線性度，該電路在轉導級採用了分佈式導數疊加（distributed derivative superposition）的技術。在切換級(switching stage)內部，使用了電感電容共振電路(LC tank)和主動負載(active load)來提高轉換增益和線性度性能。此電路最終的量測結果為：最高轉換增益-4.8 dB，3 dB頻寬為47-62 GHz，在60 GHz操作頻率下的輸入三階截斷點(IIP3)為15.2 dBm，輸入1dB壓縮點(IP1dB)為2 dBm。 最後一個部分著重於D頻段次諧波升頻器的設計。此研究使用65互補式金氧化物半導體製程製作。為了降低調變系統內部本地振盪鏈的設計難度，採用了次諧波混頻器架構以降低本地振盪鏈的操作頻率。在中頻(IF)端和本地振盪源(LO)端均使用了放大器來提升整體混頻器的轉換增益。本地振盪源端的相位耦合器的設計中，45度功率分配器採用了威金森(Wilkinson)功率分配器結合高通和低通濾波器來產生相位差。中頻端則使用了晶片外部的90度耦合器和巴倫(Balun)來產生理想的四相訊號。在射頻(RF)端，使用巴倫和威金森功率合成器將四相訊號整合成一路輸出。最終量測結果為：射頻端的 3 dB頻寬為139-161 GHz，最高轉換增益為-4.3 dB，本地振盪源端的 3 dB頻寬為67-78 GHz，中頻端的3dB頻寬為1-10 GHz。在射頻端的3 dB頻寬內的鏡像訊號抑制比（IRR）皆小於-15.5 dB。

This paper includes several sections: V-band low phase variation VGLNA, V-band high linearity down-conversion mixer, and D-band sub-harmonic IQ up-conversion mixer measurement and simulation results. The first part will focus on the design of the V-band low phase variation VGLNA. This VGLNA is primarily used in V-band phased array systems. The research is conducted using a 90-nm CMOS process. To achieve low phase variation, the circuit employs an inductive phase-inversion network to inverse the phase variation trend of the current-steering architecture's output versus the control voltage. This allows the two-stage cascaded current steering VGA to have a phase cancellation effect, thereby realizing low phase variation characteristics. Additionally, the input stage uses double-transformer-coupling (DTC) technology to enhance overall circuit gain and stability while reducing noise figure and DC power consumption. The measured maximum gain of the VGLNA is 20.7 dB, 3 dB bandwidth of 55-62 GHz, minimum noise figure of 5.3 dB, relative phase shift within the 3 dB bandwidth of 6.3 degrees, and RMS phase error of 2.45 degrees. The second part focuses on the V-band high linearity down-conversion mixer, primarily used in high-linearity receivers or demodulation systems. This research is also conducted using a 90-nm CMOS process. To enhance the overall linearity of the mixer, the circuit employs the distributed derivative superposition (DS) technique in the transconductance stage. The LC tank and active load improve the switching stage's conversion gain and linearity performance. The final measured results of this circuit are a maximum gain of -4.8 dB, a 3 dB bandwidth of 47-62 GHz, an IIP3 of 15.2 dBm at an operating frequency of 60 GHz, and an IP1dB of 2 dBm. The final part focuses on the design of the D-band sub-harmonic up-conversion mixer. To reduce the design complexity of the LO chain in the modulation system, the sub-harmonic mixer architecture is adopted to lower the operating frequency of the LO chain. Buffers are used at both the IF and LO ends to enhance the overall conversion gain of the mixer. For the LO phase coupler design, a 45-degree power divider employs a Wilkinson power divider combined with high pass and low pass filters to generate the phase difference. The IF end uses an off-chip 90-degree coupler and balun to produce the desired quadrature signals. A balun and Wilkinson power combiner at the RF end are used to integrate the quadrature signals into a single output. The final measured results are an RF 3 dB bandwidth of 139-161 GHz, a maximum conversion gain of -4.3 dB, an LO 3 dB bandwidth of 67-78 GHz, and an IF bandwidth of 1-10 GHz. The image rejection ratio (IRR) within the RF 3 dB bandwidth is less than -15.5 dB, the same as the LO bandwidth.