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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96235
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dc.contributor.advisor李建模zh_TW
dc.contributor.advisorChien-Mo Lien
dc.contributor.author劉昀昇zh_TW
dc.contributor.authorYun-Sheng Liuen
dc.date.accessioned2024-11-28T16:19:56Z-
dc.date.available2025-04-01-
dc.date.copyright2024-11-28-
dc.date.issued2024-
dc.date.submitted2024-10-15-
dc.identifier.citation[1] G. Moore, J.-H. Liao, S. McDade, and B. Verzi, “Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy,” in Proceedings of the 2015 International Conference on Microelectronic Test Structures, pp. 44–49, 2015.
[2] R. Madge, B. Benware, R. Turakhia, R. Daasch, C. Schuermyer, and J. Ruffler, “In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost,” in 2004 International Conference on Test, pp. 203–212, 2004.
[3] S. Benner and O. Boroffice, “Optimal production test times through adaptive test programming,” in Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp. 908–915, 2001.
[4] M. Chen and A. Orailoglu, “Test cost minimization through adaptive test development,” in 2008 IEEE International Conference on Computer Design, pp. 234–239, 2008.
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[6] E. Yilmaz, S. Ozev, and K. M. Butler, “Adaptive test flow for mixed-signal/rf circuits using learned information from device under test,” in 2010 IEEE International Test Conference, pp. 1–10, 2010.
[7] M. Liu, R. Pan, F. Ye, X. Li, K. Chakrabarty, and X. Gu, “Fine-grained adaptive testing based on quality prediction,” in 2018 IEEE International Test Conference (ITC), pp. 1–10, 2018.
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[12] M. Liu and K. Chakrabarty, “Adaptive methods for machine learning-based testing of integrated circuits and boards,” in 2021 IEEE International Test Conference (ITC), pp. 153–162, 2021. [13] E. Yilmaz and S. Ozev, “Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information,” in 2012 17th IEEE European Test Sym- posium (ETS), pp. 1–6, 2012.
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[19] B.-H. Hsieh, Y.-S. Liu, J. C.-M. Li, C. Nigh, M. Chern, and G. Bhargava, “Diagnosis of systematic delay failures through subset relationship analysis,” in 2023 IEEE International Test Conference (ITC), pp. 293–302, IEEE, 2023.
[20] M.-T. Wu, C.-S. Kuo, J. C.-M. Li, C. Nigh, and G. Bhargava, “Improving volume diagnosis and debug with test failure clustering and reorganization,” in 2021 IEEE International Test Conference (ITC), pp. 251–259, 2021.
[21] K. Huang, H.-G. Stratigopoulos, and S. Mir, “Fault diagnosis of analog circuits based on machine learning,” in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 1761–1766, 2010.
[22] H. H. Chen, R. Hsu, P. Yang, and J. J. Shyr, “Predicting system-level test and in-field customer failures using data mining,” in 2013 IEEE International Test Conference (ITC), pp. 1–10, 2013.
[23] D. Drmanac, N. Sumikawa, L. Winemberg, L.-C. Wang, and M. S. Abadir, “Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits,” in 2011 Design, Automation & Test in Europe, pp. 1–6, 2011.
[24] T. M. Cover, J. A. Thomas, et al., “Entropy, relative entropy and mutual information,” Elements of information theory, vol. 2, no. 1, pp. 12–13, 1991.
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[26] S. Agrahari and A. K. Singh, “Concept drift detection in data stream mining : A literature review,” Journal of King Saud University - Computer and Information Sciences, vol. 34, no. 10, Part B, pp. 9523–9540, 2022.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96235-
dc.description.abstract隨著集成電路的複雜性進步,晶圓測試面臨著平衡測試時間、測試品質和診斷信息保存的困難。一方面,我們需要高品質的晶圓測試來在早期測試階段檢測出有缺陷的晶片。另一方面,高品質的晶圓測試可能耗時較長。此外,有關有缺陷晶粒的診斷信息對於提高產量至關重要。作為回應,我們提出了一種基於機器學習模型的自適應晶圓測試方法,在測試待測晶片時使用機器學習模型。通過跳過某些測試群組,自適應方法可以在保持高品質和保存診斷信息的同時節省測試時間。自適應晶圓測試可以減少多達39%的測試時間。與傳統的晶圓測試相比,自適應晶圓測試減少了7.8倍的缺陷晶片分選和338倍的測試失效訊息損失。zh_TW
dc.description.abstractAs the complexity of integrated circuits advances, wafer sort faces the difficulty of balancing test time, test quality, and diagnostic information preservation. On the one hand, we need a high-quality wafer sort that detects defective chips at the early test stage. On the other hand, high-quality wafer sort can be time-consuming. In addition, diagnostic information about defective dies is crucial to improve the yield. In response, we propose an ML-based adaptive wafer sort using machine learning models when testing a die-under-test (DUT). By skipping some test suites, the adaptive method can save test time while retaining high quality and preserving diagnostic information. The adaptive wafer sort can reduce up to 39% of test time. The adaptive wafer sort improves bin swap and failure information loss by 7.8× and 338× compared to the traditional wafer sort.en
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dc.description.tableofcontents致謝 i
摘要 iii
Abstract iv
Contents v
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Proposed Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 Background 8
2.1 Previous works of Adaptive Tests . . . . . . . . . . . . . . . . . . . 8
2.2 ML Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Wafer Sort Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Diagnostic Information and Adaptive Test . . . . . . . . . . . . . . . 15
Chapter 3 Proposed Techniques 18
3.1 Basic Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Problem Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Offline Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.1 Low-failure-rate Test Suites Removal . . . . . . . . . . . . . . . . 24
3.4.2 Correlation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3 Training Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.4 Scored-based Models Sorting . . . . . . . . . . . . . . . . . . . . . 32
3.5 Online Deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4 Experimental Results 35
4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Models Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Test Time Reduction and Multi-site Testing . . . . . . . . . . . . . . 38
4.4 Trade-off among Test Time, Test Quality, and Diagnostic Information Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.5 Diagnostic Information Preservation . . . . . . . . . . . . . . . . . . 41
Chapter 5 Discussion 44
5.1 Model Recall and Failure Types . . . . . . . . . . . . . . . . . . . . 44
5.2 Threshold Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3 Handling Process Variations . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 6 Conclusion 49
References 51
Appendix 1 — Notations 55
Appendix 2 — Model Feature Breakdown 56
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dc.language.isoen-
dc.subject診斷資訊zh_TW
dc.subject機器學習zh_TW
dc.subject自適應測試zh_TW
dc.subject減少測試時間zh_TW
dc.subjectdiagnostic informationen
dc.subjecttest time reductionen
dc.subjectadaptive testsen
dc.subjectmachine learningen
dc.title基於機器學習的自適應晶圓級測試以保留診斷信息zh_TW
dc.titleML-based Adaptive Wafer Sort to Preserve Diagnostic Informationen
dc.typeThesis-
dc.date.schoolyear113-1-
dc.description.degree碩士-
dc.contributor.oralexamcommittee呂學坤;張益興zh_TW
dc.contributor.oralexamcommitteeShyue-Kung Lu;Yi-Shing Changen
dc.subject.keyword減少測試時間,自適應測試,機器學習,診斷資訊,zh_TW
dc.subject.keywordtest time reduction,adaptive tests,machine learning,diagnostic information,en
dc.relation.page58-
dc.identifier.doi10.6342/NTU202401650-
dc.rights.note未授權-
dc.date.accepted2024-10-15-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
Appears in Collections:電子工程學研究所

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