利用查表法之無除法器NLMS適應性濾波器實現

Abstract

隨著時代的發展，半導體技術持續進步，製程技術也逐漸縮小到數十奈米甚至更小。然而，無論製程技術進展到多少奈米，除法器在硬體設計中依然面臨諸多挑戰。除法器的運算速度相對較慢，佔用大量的硬體資源，並且消耗大量的功耗，這些因素嚴重影響了系統的性能和效能。 為了解決這些問題，本論文提出了一種近似除法的方法，即在NLMS適應性濾波器中使用LUT倒數近似法，以避免使用傳統的除法。模擬結果顯示，在NLMS演算法中分母使用LUT倒數近似法，並且輸入為6位元、輸出為4位元時，其均方誤差和頻率響應表現與使用16位元以及24位元的傳統除法器相當。硬體實現結果顯示，在相同工作頻率下，FIR架構中，LUT使用了11857個邏輯元件和2569個暫存器，與傳統除法ulp=4相比，提升了45%的吞吐量，在FOM中減少了30.5%。在IIR架構中，LUT使用21508個邏輯元件和3783個暫存器，與傳統除法ulp=4相比，提升了45%的吞吐量，在FOM中減少了30.1%。

Process technology has scaled down to tens of nanometers or smaller with the advancement of semiconductor technology. Regardless of these advancements, dividers still face many challenges in hardware design. They have relatively slow computation speeds, occupy a lot of hardware resources, and consume significant power, severely affecting system performance and efficiency. To tackle these challenges, the thesis employs an approximate division method using the LUT reciprocal approximation technique in NLMS adaptive filters as an alternative to conventional division. The simulation results indicate that when the LUT reciprocal approximation is applied in the denominator of the NLMS adaptive filter, with 6-bit input and 4-bit output, the mean square error (MSE) and frequency response performance are comparable to those achieved using a 16-bit and a 24-bit conventional divider. The hardware implementation results show that, at the same operating frequency, LUTs utilize 11857 logic elements and 2569 registers in the FIR architecture, increasing throughput by 45% and decreasing FOM by 30.5% compared to conventional division methods SRT ulp4. In the IIR architecture, LUTs similarly utilize 21508 logic elements and 3783 registers, increasing throughput by 45% and decreasing FOM by 30.1% compared to conventional division methods SRT ulp4.