原子層沉積次奈米氧化鎵應用於電晶體閘極氧化層之電性調變與分析

Abstract

隨著摩爾定律的預測，電晶體的發展一直遵循著電晶體密度約每18個月翻倍的趨勢。然而，隨著傳統電晶體尺寸的持續縮小，物理與製程上的挑戰逐漸顯現，使得電晶體的發展難以完全符合摩爾定律的預測。此外，傳統半導體材料在不同應用環境下的性能也逐漸受到限制。基於此背景，研究人員近年來積極探索新型半導體技術與材料。 目前，半導體生產以矽（Si）晶圓為主。然而，隨著開發的深入，矽的物理特性已接近其極限。在此情況下，寬能隙半導體（Wide Band Gap，WBG）應運而生，其中氧化鎵（Ga2O3）因其高達4.9eV的能隙而備受關注。Ga2O3不僅在各種功率元件中具有潛力，還在各類感測器的應用中展現出巨大潛能。 然而，作為電晶體閘極氧化層的材料，Ga2O3的應用仍在探索階段。 在這篇碩士論文中，我們利用自製的電漿輔助原子層沉積（Plasma Enhanced Atomic Layer Deposition, PEALD）設備進行Ga2O3薄膜的沉積。通過調整溫度、製程氣體流量等參數，並利用膜厚量測儀、XPS、UPS等設備對薄膜的品質進行分析。我們進一步繪製了Ga2O3薄膜與傳統矽晶圓介面的能帶圖，發現沉積次奈米級Ga2O3薄膜於閘極氧化層與矽通道之間，具有調變矽通道元件電性表現的潛力。 我們還實際展示了沉積次奈米級Ga2O3薄膜於閘極氧化層與矽通道之間的製程，並與對照組進行比較和電性分析。結果顯示，這種次奈米級Ga2O3薄膜具有調變閾值電壓、增強電流及擴展電壓運作範圍的潛力，展現出相當大的發展前景。

The development of transistors has historically followed Moore's Law, with transistor density approximately doubling every 18 months. However, as traditional transistor dimensions continue to shrink, physical and manufacturing challenges have emerged, making it increasingly difficult to maintain the pace predicted by Moore's Law. Additionally, the performance of conventional semiconductor materials is increasingly constrained in various application environments. In light of these challenges, researchers have recently been actively exploring new semiconductor technologies and materials. Currently, semiconductor production is predominantly based on silicon (Si) wafers. However, as the development of Si approaches its physical limits, wide bandgap semiconductors (WBGs) have emerged as a promising alternative. Among these, gallium oxide (Ga2O3), with a bandgap as wide as 4.9 eV, has garnered significant attention. Ga2O3 shows considerable potential not only in various power devices but also in the application of diverse sensors. Nevertheless, the application of Ga2O3 as a gate oxide layer in transistors is still under investigation. In this master's thesis, we employed a custom-built Plasma Enhanced Atomic Layer Deposition (PEALD) system to deposit Ga2O3 thin films. By adjusting parameters such as temperature and process gas flow, we analyzed the quality of the films using tools such as thickness measurement instruments, X-ray photoelectron spectroscopy (XPS), and ultraviolet photoelectron spectroscopy (UPS). We further constructed a band diagram of the interface between the Ga2O3 film and conventional Si wafers, discovering that depositing sub-nanometer Ga2O3 thin films between the gate oxide layer and the Si channel could modulate the electrical performance of Si channel devices. We also demonstrated the process of depositing sub-nanometer Ga2O3 thin films between the gate oxide layer and the Si channel and conducted comparative electrical analyses with control devices. The results indicate that such sub-nanometer Ga2O3 thin films have the potential to modulate threshold voltage, enhance current, and expand the voltage operating range, showcasing significant development potential.