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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張子璿 | zh_TW |
| dc.contributor.advisor | Tzu-Hsuan Chang | en |
| dc.contributor.author | 郭鎮宇 | zh_TW |
| dc.contributor.author | Zhen-Yu Guo | en |
| dc.date.accessioned | 2024-09-09T16:13:48Z | - |
| dc.date.available | 2024-09-10 | - |
| dc.date.copyright | 2024-09-09 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-14 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/95452 | - |
| dc.description.abstract | 隨著摩爾定律的預測，電晶體的發展一直遵循著電晶體密度約每18個月翻倍的趨勢。然而，隨著傳統電晶體尺寸的持續縮小，物理與製程上的挑戰逐漸顯現，使得電晶體的發展難以完全符合摩爾定律的預測。此外，傳統半導體材料在不同應用環境下的性能也逐漸受到限制。基於此背景，研究人員近年來積極探索新型半導體技術與材料。
目前，半導體生產以矽（Si）晶圓為主。然而，隨著開發的深入，矽的物理特性已接近其極限。在此情況下，寬能隙半導體（Wide Band Gap，WBG）應運而生，其中氧化鎵（Ga2O3）因其高達4.9eV的能隙而備受關注。Ga2O3不僅在各種功率元件中具有潛力，還在各類感測器的應用中展現出巨大潛能。 然而，作為電晶體閘極氧化層的材料，Ga2O3的應用仍在探索階段。 在這篇碩士論文中，我們利用自製的電漿輔助原子層沉積（Plasma Enhanced Atomic Layer Deposition, PEALD）設備進行Ga2O3薄膜的沉積。通過調整溫度、製程氣體流量等參數，並利用膜厚量測儀、XPS、UPS等設備對薄膜的品質進行分析。我們進一步繪製了Ga2O3薄膜與傳統矽晶圓介面的能帶圖，發現沉積次奈米級Ga2O3薄膜於閘極氧化層與矽通道之間，具有調變矽通道元件電性表現的潛力。 我們還實際展示了沉積次奈米級Ga2O3薄膜於閘極氧化層與矽通道之間的製程，並與對照組進行比較和電性分析。結果顯示，這種次奈米級Ga2O3薄膜具有調變閾值電壓、增強電流及擴展電壓運作範圍的潛力，展現出相當大的發展前景。 | zh_TW |
| dc.description.abstract | The development of transistors has historically followed Moore's Law, with transistor density approximately doubling every 18 months. However, as traditional transistor dimensions continue to shrink, physical and manufacturing challenges have emerged, making it increasingly difficult to maintain the pace predicted by Moore's Law. Additionally, the performance of conventional semiconductor materials is increasingly constrained in various application environments. In light of these challenges, researchers have recently been actively exploring new semiconductor technologies and materials.
Currently, semiconductor production is predominantly based on silicon (Si) wafers. However, as the development of Si approaches its physical limits, wide bandgap semiconductors (WBGs) have emerged as a promising alternative. Among these, gallium oxide (Ga2O3), with a bandgap as wide as 4.9 eV, has garnered significant attention. Ga2O3 shows considerable potential not only in various power devices but also in the application of diverse sensors. Nevertheless, the application of Ga2O3 as a gate oxide layer in transistors is still under investigation. In this master's thesis, we employed a custom-built Plasma Enhanced Atomic Layer Deposition (PEALD) system to deposit Ga2O3 thin films. By adjusting parameters such as temperature and process gas flow, we analyzed the quality of the films using tools such as thickness measurement instruments, X-ray photoelectron spectroscopy (XPS), and ultraviolet photoelectron spectroscopy (UPS). We further constructed a band diagram of the interface between the Ga2O3 film and conventional Si wafers, discovering that depositing sub-nanometer Ga2O3 thin films between the gate oxide layer and the Si channel could modulate the electrical performance of Si channel devices. We also demonstrated the process of depositing sub-nanometer Ga2O3 thin films between the gate oxide layer and the Si channel and conducted comparative electrical analyses with control devices. The results indicate that such sub-nanometer Ga2O3 thin films have the potential to modulate threshold voltage, enhance current, and expand the voltage operating range, showcasing significant development potential. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-09-09T16:13:48Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-09-09T16:13:48Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv 目次 vi 圖次 ix 表次 xiii Chapter 1 Introduction 1 1.1 Introduction of transistor 1 1.1.1 Moore’s Law scaling and technology node 1 1.1.2 Physical challenges 3 1.1.3 Challenges and new technology for Fabricating Transistors 4 1.2 The evolution of transistor 7 1.2.1 Planar MOSFET 7 1.2.2 FinFET 8 1.2.3 Gate-all-around FET (GAAFET) 11 1.3 From silicon to ultra-wide band gap material 12 1.3.1 SiC and GaN 13 1.3.2 Ga2O3 14 Chapter 2 Discussion of Ga2O3 15 2.1 Review of Ga2O3 15 2.2 Application of Ga2O3 18 2.3 Growth method of Ga2O3 21 2.4 To apply ALD Ga2O3 into gate oxide layer 22 Chapter 3 ALD Ga2O3 process development and material analysis 25 3.1 Atomic layer deposition 25 3.1.1 Mechanism of ALD 25 3.1.2 ALD for gate oxide and oxide semiconductor 26 3.2 Introduction of ALD Ga2O3 27 3.3 ALD Ga2O3 equipment and parameter setting 28 3.3.1 Temperature 32 3.3.2 Ionized O2 fraction 34 3.4 Material analysis 36 3.4.1 XPS 36 3.4.2 UPS 43 3.4.3 Band diagram analysis 46 3.4.4 Application into gate oxide and passivation layer 49 3.4.5 C-V analysis 50 Chapter 4 Ga2O3/Si FinFET fabrication process 54 4.1 Micro scale Ga2O3 FinFET Fabrication process flow 55 4.1.1 Layout / Mask design 57 4.1.2 Lithography and S/D define 58 4.1.3 Gate deposition and Etching 61 4.1.4 Implantation and RTA 65 4.1.5 Via and pad metal deposition and lift off 67 4.2 DC analysis 71 4.2.1 Normal nfet versus Ga2O3 nfet 71 Chapter 5 Conclusion and Future Works 73 5.1 Conclusion 73 5.2 Future work 74 Reference 75 | - |
| dc.language.iso | en | - |
| dc.subject | 次奈米 | zh_TW |
| dc.subject | 氧化鎵 | zh_TW |
| dc.subject | 閘極氧化層 | zh_TW |
| dc.subject | 寬能隙半導體 | zh_TW |
| dc.subject | 電漿輔助原子層沉積 | zh_TW |
| dc.subject | Wide Bandgap Semiconductors | en |
| dc.subject | Plasma-enhanced Atomic Layer Deposition | en |
| dc.subject | Gallium Oxide | en |
| dc.subject | Gate Oxide Layer | en |
| dc.subject | sub-nanometer | en |
| dc.title | 原子層沉積次奈米氧化鎵應用於電晶體閘極氧化層之電性調變與分析 | zh_TW |
| dc.title | Electrical Modulation and Analysis of Sub-Nanometer Gallium Oxide by Plasma-Enhanced Atomic Layer Deposition Applied to Transistor Gate Oxide Layers | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳敏璋;吳肇欣;林致廷 | zh_TW |
| dc.contributor.oralexamcommittee | Miin-Jang Chen;Chao-Hsin Wu;Chih-Ting Lin | en |
| dc.subject.keyword | 寬能隙半導體,電漿輔助原子層沉積,氧化鎵,閘極氧化層,次奈米, | zh_TW |
| dc.subject.keyword | Wide Bandgap Semiconductors,Plasma-enhanced Atomic Layer Deposition,Gallium Oxide,Gate Oxide Layer,sub-nanometer, | en |
| dc.relation.page | 80 | - |
| dc.identifier.doi | 10.6342/NTU202404231 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-08-14 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-08-22 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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