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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Sin-Jhih Li | en |
dc.contributor.author | 黎信志 | zh_TW |
dc.date.accessioned | 2021-05-20T20:26:34Z | - |
dc.date.available | 2013-09-02 | |
dc.date.available | 2021-05-20T20:26:34Z | - |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-25 | |
dc.identifier.citation | [1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
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H. van de Beek and et al., “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, November 2004. [14] C. Cao and et al., “A 50-GHz Phase-Locked Loop in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1649-1656, August 2007. [15] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional phase-frequency detector,” IEEE Journal of Solid-State Circuits, vol. 25, no. 8, pp. 1019-1022, August 1990. [16] C. S. Vaucher, Architectures for RF frequency synthesizers. Boston, MA: Kluwer, 2002. [17] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, February 1998. [18] H.-I. Cong and et al., “A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1946-1953, December 2001. [19] Jri Lee, M. Liu, and H. Wang, 'A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique, ' IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, June 2008. [20] Y. Tang, M. Ismail and S. Bibyk, “Adaptive Miller capacitor multiplier for compact on-chip PLL filter,” IEE Electronics Letters, vol. 39, no. 1, pp. 43-45, December 2003. [21] G. A. R. Mora, “Active capacitor multiplier in Miller-compensated circuits,” IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 26-32, January 2000. [22] Y. Koo and et al., “A full integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems,” IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002. [23] C.-W. Lo and H.-C. Luong, “A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications,” IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 459-470, April 2002. [24] J. Craninckx and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, December 1998. [25] A. Maxim and M. Gheorghe., “A sub-1psrms jitter 1-5GHz 0.13-μm CMOS PLL using a passive feedforward loop filter with noiseless resistor multiplication,” IEEE Radio Frequency integrated Circuits Symposium, pp. 207-210, June 2005. [26] A. Maxim, “A 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator,” IEEE Solid-State Circuits Conference, pp. 363-366, September 2004. [27] Mounir Meghelli and et al., “A 0.18-μm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems,” IEEE J. Solid-State Circuits, vol. 38, pp. 2147-2154, December. 2003. [28] Hai Tao, and et al., “40-43Gb/s OC-768 16:1 MUX/CMU Chipset with SFD-5 Compliance,” IEEE J. Solid-State Circuits, vol. 38, pp. 2169-2180, December. 2003. [29] Y-H. Chen, and et al., 'A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18-μm CMOS,' IEEE Transactions on microwave theory and techniques, vol. 56, no. 5, pp. 1043-1051, May 2008. [30] M.-D. Tsai, Y.-H. Wang, “A 5-GHz low phase noise differential CMOS VCO,” IEEE Microw. Wireless Compon. Lett., vol.15, no. 5, pp.327-329, May 2005. [31] X. Li, S. Shekhar, and D. J. Allstot, “Gm-boosting common-gate LNA and deiierential Colpitts VCO/QVCO in 0.18-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, December. 2005. [32] R. Aparicio and A. Hajimiri, “A noise-shifting differential Colpitts VCO,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1728-1736, December. 2002. [33] E. Hegazi, H.Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, December. 2001. [34] J-C. Chien, and L-H. Lu, “40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS,” ISSCC Dig. Tech. Papers, pp.544-621, February. 2007. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9519 | - |
dc.description.abstract | 本篇論文主題主要在介紹高頻鎖相迴路的設計與實作。論文中討論了數個方法以改善在高頻鎖相迴路中時脈擾動的情形。論文共分為六個章節,首先第一章對此篇論文作概略性的介紹,第二章則回顧鎖相迴路的背景知識。
第三章提出了一個使用多重相位控制的鎖相迴路架構。藉由此架構可有效抑制壓控震盪器控制電壓上來自參考時脈的週期性擾動,進而減少時脈鎖定時的擾動現象。此迴路架構使用了0.18-μm標準互補式金氧半導體製程加以實現,同時量測結果也會於本章呈現。 第四章將實現一個雙迴路的鎖相迴路架構。此架構可等效上減少迴路濾波器所需要的電容面積,故有助於單晶積體電路的整合。由於來自晶片外的元件雜訊減少了,時脈鎖定時的雜訊擾動現象也能因此有所改善。此鎖相迴路設計使用了0.18-μm標準互補式金氧半導體製程實作並且加以量測。 第五章將討論一個30-GHz的鎖相迴路設計。此設計採用了改良式的Colpitts壓控震盪器以減少壓控震盪本身所產生雜訊並使用了regenerative除頻器來增加如此高速下時脈信號的除頻範圍。此章將詳述此30-GHz鎖相迴路之設計流程與模擬結果。 | zh_TW |
dc.description.abstract | This thesis illustrates the implementation of the high frequency phase-locked loops (PLLs). In order to reduce the output jitter, several strategies are presented, which are suitable for high speed PLL design. The thesis is organized as six chapters. The first chapter is the introduction. In chapter 2, the background knowledge for the PLL design is overviewed.
In chapter 3, a PLL with multi-phase control architecture is proposed. Since the proposed architecture effectively suppresses the ripple of the controlled voltage, the jitter resulted from the reference feedthrough is decreased. The circuit is implemented with 0.18-μm CMOS technologies and the measured resulted is also included in this chapter. In chapter 4, a PLL with a compact loop filter is presented. The presented architecture is well suited for the implementation of fully integrated PLLs since the required capacitance in the loop filter can be substantially reduced. The jitter performance will be improved because of the absence of offchip components. The circuit is also realized with 0.18-μm CMOS process and the measured resulted is also included in this chapter. In chapter 5, a PLL operated at 30-GHz is designed and simulated. The modified Colpitts VCO is adopted for the reduction of the VCO noise. A regenerative frequency divider is also employed to widen the dividable range at such high frequency. The design process and the simulation results will be illustrated in this chapter. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T20:26:34Z (GMT). No. of bitstreams: 1 ntu-97-R95943026-1.pdf: 1473445 bytes, checksum: af3022d90aba21c396998f6ae1d8c7c7 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Acknowledgement........................................I
Abstract................................................III Table of Contents.......................................VII List of Figures..........................................XI List of Tables...........................................XV CHAPTER 1 INTRODUCTION....................................1 1.1 MOTIVATION............................................1 1.2 THESIS OVERVIEW.......................................2 CHAPTER 2 BACKGROUND......................................5 2.1 BASIC CONCEPTS OF THE PLL.............................5 2.2 BUIDING BLOCKS OF THE PLL.............................6 2.2.1 THE PHASE AND FREQUENCY DETECTOR (PFD) AND CHARGE PUMP (CP).................................................6 2.2.2 VOLTAGE-CONTROLLED OSCILLATOR (VCO).................9 2.2.3 FREQUENCY DIVIDER (FD).............................10 2.3 THE LINEAR MODEL FOR THE PLL.........................10 2.4 JITTER...............................................14 CHAPTER 3 A LOW-JITTER 10-GHZ PHASE-LOCKED LOOP WITH THE MULTI-PHASE CONTROL......................................17 3.1 INTRODUCTION.........................................17 3.2 THE PROPOSED PLL ARCHITECTURE........................19 3.2.1 DISTRIBUTED PFD AND CP WITH MULTI-PHASE CONTROL....20 3.2.2 DECOMPOSITION OF FREQUENCY AND PHASE DETECTION.....23 3.3 CIRCUIT IMPLEMENTATION...............................25 3.4 EXPERIMENTAL RESULTS.................................29 3.5 CONCLUSION...........................................32 CHAPTER 4 A 10-GHZ PHASE-LOCKED LOOP WITH A COMPACT LOOP FILTER...................................................35 4.1 INTRODUCTION.........................................36 4.2 THE PROPOSED PLL ARCHITETURE.........................37 4.2.1 COMPACT-LOOP-FILTER TECHNIQUE......................37 4.2.2 PD/FD DECOMPOSTION.................................41 4.2.3 DESIGN TRADEOFF....................................43 4.3 CIRCUIT IMPLEMENTATION...............................45 4.4 EXPERIMENTAL RESULTS.................................49 4.5 CONCLUSION...........................................52 CHAPTER 5 A 30-GHZ PHASE-LOCKED LOOP.....................53 5.1 INTRODUCTION.........................................53 5.2 ARCHITECTURE.........................................54 5.3 CIRCUIT IMPLEMENTATION...............................55 5.3.1 THE MODIFIED COLPITTS VCO..........................55 5.3.2 REGENERATIVE FREQUENCY DIVIDER.....................57 5.4 SIMULATION RESULTS...................................59 5.4.1 THE BEHAVIOR MODEL SIMULATION......................59 5.4.2 THE MODIFIED COLPITTS VCO AND THE REGENERATIVE FREQUENCY DIVIDER...........................61 5.5 CONCLUSION...........................................62 CHAPTER 6 CONCLUSION.....................................65 BIBLIOGRAPHY.............................................67 | |
dc.language.iso | en | |
dc.title | 高頻CMOS鎖相迴路之設計與實現 | zh_TW |
dc.title | Design and Implementation of High-frequency CMOS Phase-locked Loops | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭建男,陳巍仁,鄭裕庭 | |
dc.subject.keyword | 高頻鎖相迴路,頻率偵測器,多相位控制, | zh_TW |
dc.subject.keyword | Phase-locked loop,PD,FD,multi-phased control, | en |
dc.relation.page | 70 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2008-08-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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