用於開發設計驗證演算法的通用驗證框架

Abstract

隨著積體電路(IC)複雜度和規模的增加，開法有效率的驗證演算法已成為 IC 設計驗證中重要的一部分。儘管現有的開源驗證框架，如 ABC 和 Yosys 已經非 常成熟，但在易用性、文件編寫、程式可讀性和擴充性方面存在缺點，導致實作 地效率較低。本論文提出了一個新的通用驗證框架，該框架在整合這些工具的同 時，解決了它們原有的限制。我們的框架有以下幾個主要的貢獻。通過利用 ABC 和 Yosys 的功能，我們簡化了語法分析和合成階段，並提供了一個環境來擴充外 部引擎。我們實現了一個電路(DUV)的表示，儲存在兩個引擎(ABC, Yosys) 和我們的資料結構 (Circuit)。此外，我們開發了通用引擎，改善了 DUV 和驗證工 具之間的資料傳輸介面。我們還使用命令列介面，以操作我們框架中的功能。實 驗結果表明，我們的方法顯著提高了演算法的實作效率，對設計驗證領域做出了 重大貢獻。

Developing efficient verification algorithms has become essential in the IC design flow with the increasing complexity and scale of integrated circuits. Existing open-source verification frameworks, such as ABC and Yosys, though beneficial, present challenges in user-friendliness, documentation, coding complexity, and extensibility, leading to inefficiencies. This thesis proposes a new general-purpose verification framework that integrates these tools while addressing their limitations. Our framework introduces several key contributions. By leveraging the capabilities of ABC and Yosys, we streamline the parsing and synthesis phases and provide an extensible environment for enhancing external engines. We implement a representation of the Design Under Verification (DUV), managing its information through two engines and our data structure, Circuit Manager. Additionally, we develop utility engines that improve communication and interface mechanisms between the DUV and verification tools. Furthermore, we introduce the command-line interface that facilitates effective communication between the applications and algorithms in our framework. Experimental results demonstrate that our method significantly improves implementation efficiency and substantially contributes to the field of design verification.