應用等效原理和格林第三恆等式的分層電容宏觀建模

Abstract

隨著科技的快速發展，積體電路（IC）設計領域中的晶片持續微型化且複雜性增加，使封裝結構也變得更加精密且多層次化，為現代電子設備帶來性能、功耗、體積等多方面的優勢，也推動了半導體行業的進步和發展。 然而，這些進步也加強了對精確電氣分析的需求，特別是在寄生電容提取方面。準確建模這些寄生效應對於確保信號完整性及優化整體電路性能至關重要。此外，隨著矽智財的重要性日益突出，防止非法複製和利用已成為一個關鍵問題。因此，開發同時解決多層寄生電容提取技術和矽智財保護需求的方法具有重大意義。 為了解決這些挑戰，本研究利用邊界元素法，並提出使用電磁學中的等效原理，對各層進行宏觀建模，並利用分層寄生提取技術來獲取電容。該算法不僅能夠準確計算複雜結構中的電容值，還能通過將原始佈局轉換為等效封閉曲面上的假想電荷，以取代其影響，有效的保護內部資訊。通過一系列測試和應用該算法，結果顯示我們的方法在電容提取上，在精度方面有卓越的表現，同時在計算效率和矽智財保護方面也具有顯著優勢。

With rapid advancements in technology, the continuous miniaturization and increasing complexity of chips in the field of integrated circuit (IC) design have also made packaging structures more intricate and multilayered. These advancements provide significant advantages in performance, power consumption, and size for modern electronic devices, driving progress and development in the semiconductor industry. However, these advancements also heighten the need for precise electrical analysis, particularly in the extraction of parasitic capacitance. Accurate modeling of these parasitic effects is crucial for ensuring signal integrity and optimizing overall circuit performance. Additionally, with the growing importance of silicon intellectual property (IP), preventing illegal copying and exploitation has become a critical issue. Therefore, developing methodologies that address both the technical challenges of multilayer parasitic capacitance extraction and the need for silicon IP protection is of paramount importance. To address these challenges, this study utilizes the boundary element method (BEM), and proposes using the equivalence principle in electromagnetics to perform macromodeling for each layer, utilizing hierarchical parasitic extraction techniques to obtain capacitance. This algorithm not only accurately calculates capacitance in complex structures but also protects internal information by transforming the original layout into equivalent imaginary charges on a closed surface. Through a series of tests and applications of this algorithm, the results demonstrate that our method excels in accuracy for capacitance extraction, and offers significant advantages in computational efficiency and silicon IP protection.