考量動態矽穿孔規劃之多層重分佈層繞線系統

Abstract

於先進封裝中，多層重分布層(redistribution layer)能提供不同晶片之間的連線。多層重分布層中，每層繞線層則通過貫孔(via)在各層之間進行信號傳遞。然而現行的重分布層繞線器多在繞線開始之前便決定貫孔的位置，此舉將限制設計的自由度，造成較長的總線長、更長的求解時間與較差的整體繞線結果。本論文提出於繞線過程中動態插入貫孔的90-135 度繞線流程與相應的資源估計方式，提供更高的設計自由度從而提升繞線品質。實驗結果顯示此方法比起最先進的90-135 度封裝繞線器有著可觀的線長優化與顯著的加速；即便相較最先進的任意角度封裝繞線器也能在較嚴格的限制下獲得線長縮減與大量加速。

In modern advanced packaging, redistribution layers (RDLs) are often used for signal transmission among chips, and vias are used for communication among different layers. Most existing RDL routers perform via planning before routing. However, since vias can be placed at arbitrary locations under the irregular via structure, via planning limits the solution space and reduces layout flexibility. This thesis proposes a new flow with a novel routing graph model for 90- and 135-degree routing, which allows dynamic via insertion during routing. The proposed algorithm enlarges the solution space by providing more choices during path-finding, achieving higher routing quality. The experimental results based on commonly used benchmark suites show that our router achieves shorter wirelength and runtime than state-of-the-art works, including an any-angle router.