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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 莊哲維 | zh_TW |
| dc.contributor.author | Je-Wei Chuang | en |
| dc.date.accessioned | 2024-08-15T16:59:06Z | - |
| dc.date.available | 2024-08-16 | - |
| dc.date.copyright | 2024-08-15 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-01 | - |
| dc.identifier.citation | [1] Different Types of Shielding in Analog Layouts to Consider for PCB Design. [Online]. Available: https://resources.pcb.cadence.com/layout-and-routing/2021-different-types-of-shielding-in-analog-layouts-to-consider-for-pcb-design
[2] Y.-J. Cai, Simultaneous Pre- and Free-Assignment Net Routing for Multiple Redistribution Layers with Irregular Vias. Graduate Institute of Electronics Engineering, National Taiwan University, 2020. [3] Y.-J. Cai, Y. Hsu, and Y.-W. Chang, “Simultaneous Pre- and Free-Assignment Routing for Multiple Redistribution Layers with Irregular Vias,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1147–1152, San Francisco, CA, December 2021. [4] H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Wafer Level Chip Scale Package Copper Pillar Probing,” in Proceedings of IEEE International Test Conference, pp. 1–6, Seattle, WA, October 2014. [5] Y.-T. Chen, Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. Graduate Institute of Electronics Engineering, National Taiwan University, 2022. [6] Y.-T. Chen and Y.-W. Chang, “Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–6, San Diego, CA, November 2022. [7] M.-H. Chung, J.-W. Chuang, and Y.-W. Chang, “Any-Angle Routing for Redistribution Layers in 2.5D IC Packages,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, San Francisco, CA, July 2023. [8] J.-W. Fang and Y.-W. Chang, “Area-I/O Flip-Chip Routing for Chip- Package Co-Design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 518–522, San Jose, CA, November 2008. [9] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 606–611, San Diego, CA, June 2007. [10] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, “A Network-Flow- Based RDL Routing Algorithmz for Flip-Chip Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1417–1429, 2007. [11] J.-W. Fang, I.-J. Lin, P.-H. Yuh, Y.-W. Chang, and J.-H. Wang, “A Routing Algorithm for Flip-Chip Design,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 752–757, San Jose, CA, November 2005. [12] J.-W. Fang, M. D. F.Wong, and Y.-W. Chang, “Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 336–339, San Francisco, CA, July 2009. [13] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer-Linear-Programming- Based Routing Algorithm for Flip-Chip Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 98–110, 2009. [14] P. E. Hart, N. J. Nilsson, and B. Raphael, “A Formal Basis for the Heuristic Determination of Minimum Cost Paths,” IEEE Transactions on Systems Science and Cybernetics, vol. 4, no. 2, pp. 100–107, 1968. [15] Y.-C. Huang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Efficient Probing Schemes for Fine-Pitch Pads of InFO Wafer-Level Chip-Scale Package,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, Austin, TX, June 2016. [16] P.-W. Lee, H.-C. Lee, Y.-K. Ho, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, “Obstacle Avoiding Free-Assignment Routing for Flip-Chip Designs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1088–1093, San Francisco, CA, June 2012. [17] B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, “Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 1–6, Austin, TX, November 2016. [18] C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, “An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 6, pp. 878–889, 2012. [19] C. C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T.Wang, S.-P. Jeng, and D. C. H. Yu, “High-Performance Integrated Fan-OutWafer Level Packaging (InFO-WLP): Technology and System Integration,” in Proceedings of IEEE International Electron Devices Meeting, pp. 14.1.1–14.1.4, San Francisco, CA, December 2012. [20] X. Liu, Y. Zhang, G. K. Yeap, C. Chu, J. Sun, and X. Zeng, “Global Routing and Track Assignment for Flip-Chip Designs,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 90–93, Anaheim, CA, July 2010. [21] S.-R. Nie, Y-Architecture-Based Flip-Chip Routing with Dynamic Programming-Based Bend Minimization. Graduate Institute of Electronics Engineering, National Taiwan University, 2022. [22] S.-R. Nie, Y.-T. Chen, and Y.-W. Chang, “Y-Architecture-Based Flip-Chip Routing with Dynamic Programming-Based Bend Minimization.” in Proceedings of ACM/IEEE Design Automation Conference, pp. 955–960, San Francisco, CA, July 2022. [23] H.-P. Pu, H. Kuo, C. Liu, and C. Douglas, “A Novel Submicron Polymer Re- Distribution Layer Technology for Advanced InFO Packaging,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 45–51, San Diego, CA, June 2018. [24] C.-F. Tseng, C.-S. Liu, C.-H. We, and D. Yu, “InFO (Wafer Level Integrated Fan-Out) Technology,” in Proceedings of IEEE Electronic Components and Technology Conference, pp. 1–6, Las Vegas, NV, June 2016. [25] H.-T. Wen, Via-Based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. Graduate Institute of Electronics Engineering, National Taiwan University, 2020. [26] H.-T. Wen, Y.-J. Cai, Y. Hsu, and Y.-W. Chang, “Via-Based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures,” in Proceedings of ACM/IEEE Design Automation Conference, pp. 1–6, San Francisco, CA, July 2020. [27] ——, “Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5554–5567, 2022. [28] T. Yan and M. D. F. Wong, “Correctly Modeling the Diagonal Capacity in Escape Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 285–293, 2012. [29] D. Yu, “A New Integration Technology Platform: Integrated Fan-Out Wafer- Level-Packaging for Mobile Applications,” in Proceedings of Symposium on VLSI Technology, pp. T46–T47, Kyoto, June 2015. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94350 | - |
| dc.description.abstract | 於先進封裝中，多層重分布層(redistribution layer)能提供不同晶片之間的連線。多層重分布層中，每層繞線層則通過貫孔(via)在各層之間進行信號傳遞。然而現行的重分布層繞線器多在繞線開始之前便決定貫孔的位置，此舉將限制設計的自由度，造成較長的總線長、更長的求解時間與較差的整體繞線結果。本論文提出於繞線過程中動態插入貫孔的90-135 度繞線流程與相應的資源估計方式，提供更高的設計自由度從而提升繞線品質。實驗結果顯示此方法比起最先進的90-135 度封裝繞線器有著可觀的線長優化與顯著的加速；即便相較最先進的任意角度封裝繞線器也能在較嚴格的限制下獲得線長縮減與大量加速。 | zh_TW |
| dc.description.abstract | In modern advanced packaging, redistribution layers (RDLs) are often used for signal transmission among chips, and vias are used for communication among different layers. Most existing RDL routers perform via planning before routing. However, since vias can be placed at arbitrary locations under the irregular via structure, via planning limits the solution space and reduces layout flexibility. This thesis proposes a new flow with a novel routing graph model for 90- and 135-degree routing, which allows dynamic via insertion during routing. The proposed algorithm enlarges the solution space by providing more choices during path-finding, achieving higher routing quality. The experimental results based on commonly used benchmark suites show that our router achieves shorter wirelength and runtime than state-of-the-art works, including an any-angle router. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-15T16:59:05Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-15T16:59:06Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgement iii
Abstract (Chinese) iv Abstract v List of Tables viii List of Figures ix Chapter 1. Introduction 1 1.1 Integrated Fan-Out Structure . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Classification of Traditional RDL Routing . . . . . . . . . . . . . . . . . 3 1.3 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 Single-Layer RDL Routing . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1.1 Free-Assignment RDL Routing . . . . . . . . . . . . . . . 5 1.3.1.2 Pre-Assignment RDL Routing . . . . . . . . . . . . . . . . 8 1.3.2 Multi-Layer RDL Routing . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2.1 Layer Assignment Approach . . . . . . . . . . . . . . . . . 10 1.3.2.2 Irregular Via Approach . . . . . . . . . . . . . . . . . . . . 10 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 2. Preliminaries 17 2.1 Notations and Terminologies . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 RDL Routing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Chapter 3. Our Proposed Algorithm 19 3.1 Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 Routing Region Partitioning . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 Routing Graph Construction . . . . . . . . . . . . . . . . . . . . . 21 3.2 Global Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.1 Constrained A*-search . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 Backtracing and Sequence Determination . . . . . . . . . . . . . . 30 3.3 Detailed Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter 4. Experimental Results 35 4.1 Experimental Environment Setup . . . . . . . . . . . . . . . . . . . . . . 35 4.2 Results and Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 Comparison with the State-of-the-Art Traditional RDL Routers . . 36 4.2.2 Comparison with the State-of-the-Art Any-Angle RDL Router . . 37 4.2.3 Result Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.3.1 Wirelength Analysis . . . . . . . . . . . . . . . . . . . . . 44 4.2.3.2 Runtime Analysis . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Chapter 5. Conclusions and Future Work 48 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bibliography 52 Publication List 57 | - |
| dc.language.iso | en | - |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | 異質整合 | zh_TW |
| dc.subject | 重分佈層繞線 | zh_TW |
| dc.subject | 不規則矽穿孔結構 | zh_TW |
| dc.subject | Heterogeneous Integration | en |
| dc.subject | Redistribution Layer Routing | en |
| dc.subject | Physical Design | en |
| dc.subject | Irregular Via Structure | en |
| dc.title | 考量動態矽穿孔規劃之多層重分佈層繞線系統 | zh_TW |
| dc.title | Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江蕙如;黃婷婷;方劭云 | zh_TW |
| dc.contributor.oralexamcommittee | Iris Hui-Ru Jiang;Ting-Ting Hwang;Shao-Yun Fang | en |
| dc.subject.keyword | 實體設計,異質整合,重分佈層繞線,不規則矽穿孔結構, | zh_TW |
| dc.subject.keyword | Physical Design,Heterogeneous Integration,Redistribution Layer Routing,Irregular Via Structure, | en |
| dc.relation.page | 57 | - |
| dc.identifier.doi | 10.6342/NTU202402778 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-08-05 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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