利用約束測試模式和斷言驗證進行 RTL Bug 自動定位

Abstract

由於 IC 設計規模和複雜度的不斷增長，RTL 設計中的除錯變得越來越具有挑戰性。傳統上，工程師會生成測試模式並分析密集的波形文件，以追踪模擬結果，並與參考模型的正確結果進行比較。這個過程非常耗時且困難，因為涉及的信號眾多，包括輸入信號、輸出信號、內部信號和存儲器端口信號。 本論文介紹了我們的錯誤定位工具，可以自動過濾不相關的信號並突出顯示最有可能與錯誤相關的信號。通過根據信號的懷疑程度進行排序，並識別這些信號影響條件語句的控制路徑，該工具引導工程師找到最可能的問題區域。這顯著減少了除錯的時間和精力，使工程師能夠專注於最相關的信號和控制路徑，從而簡化了除錯密集波形和廣泛信號數據的複雜任務。這種方法將傳統上艱巨的 RTL 除錯任務轉變為更加可管理和高效的過程。

Debugging in RTL design is increasingly challenging due to the growing scale and complexity of IC designs. Traditionally, designers generate test patterns and analyze dense waveform files to trace simulation results and compare them with the golden results from a reference model. This process is time-consuming and difficult because of the numerous signals involved, including input, output, internal, and memory port signals. This thesis introduces a novel bug localization tool that automates the filtering of unrelated signals and highlights those most likely associated with bugs. By ranking signals based on their suspected degrees and identifying the control paths where these signals influence conditional statements, the tool guides designers to the most likely problem areas. This significantly reduces debugging time and effort by allowing designers to focus on the most relevant signals and control paths, thereby simplifying the complex task of debugging dense waveforms and extensive signal data. This approach transforms RTL debugging from a traditionally arduous task into a more manageable and efficient process.