一個具有超寬輸出頻率範圍的CMOS 鎖相迴路

Abstract

在當今的多頻多模通信系統中，一個體積小巧、靈活性高且具有高頻譜純度的時脈產生器是不可或缺的。由於其穩定性高、佔用空間小，第一類鎖相迴路(Type-I PLL) 近來已成為許多研究的焦點。然而，第一類鎖相迴路的鎖定範圍受到限制，這不僅使得其在實際應用中無法確保在製程、電壓、溫度變異下仍能成功鎖定，也限制了其作為寬調變範圍(tuning range)時脈產生器的應用。 本論文提出了一個頻帶選擇機制並設計了相應的頻帶選擇迴路。該迴路防止了第一類鎖相迴路脫鎖，並克服了鎖定範圍和參考突波之間的取捨。藉由頻帶選擇迴路的輔助，本論文實現了一個寬調變範圍的第一類鎖相迴路。該晶片採用TSMC 180-nm CMOS 製程實現，核心電路面積為0.12 mm2，操作電壓為1.8 V，輸出頻率範圍為840 - 2240 MHz，提供了超過90%的調變範圍。當輸入參考頻率為10 MHz，輸出頻率為2240 MHz 時，在1-MHz 頻率偏移的地方，相位雜訊為-91.7 dBc/Hz，參考突波為-50 dBc。在論文的最後，對該晶片進行了優化，計算出了最佳化的參數設計及系統頻率規劃。 此外，本文提出的頻帶選擇迴路易於適應不同的製程，並有望在未來與基於單元(cell-based)的設計流程結合，以簡化設計複雜性。

In today’s multi-band and multi-mode communication systems, a compact, flexible, and high-spectral purity clock generator is indispensable. Due to its high stability and small footprint, the type-I PLL has recently become the focus of much research. However, the acquisition range of Type-I PLLs is limited. This not only prevents them from reliably locking under process, voltage, and temperature variations in real-world applications but also restricts their use as wide-tuning range clock generators. This paper proposes a band-selecting mechanism and designs a corresponding band-selecting loop. The loop prevents the type-I PLL from unlocking and overcomes the trade-off between the acquisition range and the reference spur. With the assistance of the band-selecting loop, this paper realizes a wide tuning range type-I PLL. The chip is implemented in a TSMC 180-nm CMOS process, with a core circuit area of 0.12 mm2, operating at 1.8 V. The output frequency range is 840 - 2240 MHz, providing over 90% of the tuning range. At an input reference frequency of 10 MHz and an output frequency of 2240 MHz, the phase noise at 1 MHz frequency offset is −91.7 dBc/Hz, and the reference spur is −50 dBc. In the final section, the optimal parameter design and system frequency planning are calculated. Furthermore, the band-selecting loop proposed in this paper is easily adaptable to different processes and is expected to be combined with cell-based design flow in the future to simplify the design complexity.