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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9337完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Jhih-Siang Su | en |
| dc.contributor.author | 蘇稚翔 | zh_TW |
| dc.date.accessioned | 2021-05-20T20:18:07Z | - |
| dc.date.available | 2014-07-16 | |
| dc.date.available | 2021-05-20T20:18:07Z | - |
| dc.date.copyright | 2009-07-16 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-06-29 | |
| dc.identifier.citation | [2.1]Y.G.Chen and J. B. Kuo “Analytical Drain Current Model for
Short-Channel Fully-Depleted Ultrathin SILICON-ON-INSULATOR NMOS Device”Sol St Elec,pp.2051-2057,Dec 1995. [2.2]S.Y.Ma and J. B. Kuo,Jap.J.appl.Phys.33,550(1994) [2.3]S.Y.Ma and J. B. Kuo,Jap.J.appl.Phys.33 (1994) [2.4] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. [2.5] J. B. Kuo, “Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2001. [2.6] I. S. Lin, J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai,and M. Ma, “Breakdown behavior of 40-nm PD-SOI NMOS considering STI-induced mechanical stress effect,” IEEE Electron Device Letts, pp.612-614,June 2008. [2.7] BSIM4 by The Device Group Department of EECSUC Berkeley “http://www-device.eecs.berkeley.edu/~bsim3/bsim4_intro.html” [2.8] Philips Bipolar Transistor Level 504 by Mextram [3.1] R.Howes and W.Redman-White,”A Small-Signal Model for the Frequency Dependent Drain Admittance in Floating-Substrate MOSFET’s”IEDM Dig.,109-112(1996) [3.2] J. B. Kuo,“Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2001. [3.3] Y.Omura and K.Izumi, “Physical Background of Substrate Current Characteristics and Hot-Carrier Immunity in Short-Channel Ultrathin-Film MOSFET’s/SIMOX,” IEEE Trans.Elec.Dev.,41(3),352-358(1994) [3.4]Y.G.Chen and J. B. Kuo “Analytical Drain Current Model for Short-Channel Fully-Depleted Ultrathin SILICON-ON-INSULATOR NMOS Device”Sol St Elec,pp.2051-2057,Dec 1995. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9337 | - |
| dc.description.abstract | 本篇論文討論一個有浮動基體效應(Floating-Body-Effect)的部份解離絕緣體上矽N型金氧半元件(PD-SOI),透過雙載子電晶體(BJT) / 金氧半元件(MOS)方式去建立SPICE的模型。先在第一章簡介絕緣體上矽金氧半元件(SOI MOS Device)及其元件特性。然後在第二章描述電流傳導機制和部份解離絕緣體上矽N型金氧半元件(PD-SOI MOS Device),且使用雙載子電晶體(BJT) / 金氧半元件(MOS)的方式去建立SPICE的電流模型。第三章藉由量測的資料與模擬的結果,可以驗證使用雙載子電晶體(BJT) / 金氧半元件(MOS)的架構,對有無改良寄生雙載子電晶體電流回饋(K')到絕緣體上矽金氧半元件(SOI)中高電場區域、和高電場區域有多少電流回饋(K)到下面的寄生雙載子電晶體的準確性。而模擬出來的結果可以得出有寄生雙載子電晶體電流回饋(K'=0.99),在Gate Voltage小時,有足夠的固撞擊游離(impact ionization)電流來影響崩潰電壓。第四章為總結和未來工作。 | zh_TW |
| dc.description.abstract | This thesis reports modeling the floating-body-effect-related breakdown and the kink behavior of 40nm PD SOI NMOS device via the SPICE BJT/MOS model approach。First, in Chapter 1 introduction of PD SOI NMOS device is introduced。Then in Chapter 2 the current conduction mechanism of the PD-SOI NMOS device is described, followed by the SPICE BJT/MOS models。In Chapter 3, effectiveness of the BJT/MOS models approach is evaluated for nanometer PD-SOI NMOS devices via SPICE simulation result. As verified by the experimentally measured data and the 2D simulation results, this compact SOI model provides an accurate prediction. Chapter 4 is conclusion and future work。 | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T20:18:07Z (GMT). No. of bitstreams: 1 ntu-98-R96943096-1.pdf: 4238095 bytes, checksum: d23abd3deee9a29b303081d651c4986e (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
致謝 iii 中文摘要 iv ABSTRACT v 目錄 vi 圖目錄 viii Chapter1導論 1 1.1科技進步和模型發展之間的競賽 1 1.2 SOI簡介 3 1.3部分解離絕緣體上矽元件( PD SOI ) 浮動基體( FLOATING BODY )效應 4 1.4論文架構 7 Chapter 2 8 透過SPICE的雙載子電晶體/金氧半元件架構建立部分解離絕緣體上矽金氧半元件模型 8 2.1當前絕緣體上矽的SPICE模型(CURRENT SOI SPICE MODEL) 8 2.2模型發展 (MODEL DEVELOPMENT) 9 2.2.1飽和區電流傳導機制 9 2.2.2簡介雙載子電晶體/金氧半元件架構 11 2.2.3雙載子電晶體 / 金氧半元件電流模型 14 2.3利用SPICE雙載子電晶體/金氧半元件模型方法模擬 21 2.3.1模擬驗證 21 2.3.2結論 23 2.4參考文獻 24 Chapter 3利用SPICE模擬雙載子電晶體/金氧半元件模型對奈米級部分解離絕緣體上矽N型金氧半元件之分析 25 3.1簡介模型內部參數K與K’ 25 3.2模擬不同K’之分析 26 3.3模擬不同K之分析 33 3.4結論 39 3.5參考文獻 40 Chapter 4 41 總結41 | |
| dc.language.iso | zh-TW | |
| dc.title | 利用SPICE雙載子電晶體/金氧半元件模型方法建立40奈米部分解離絕緣體上N型矽金氧半元件浮動基體效應產生的崩潰與突增行為 | zh_TW |
| dc.title | Modeling the Floating-Body-Effect-Related Breakdown and the Kink Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 賴飛羆,林吉聰,陳正雄,蔡成宗 | |
| dc.subject.keyword | 部分解離絕緣體上N型矽金氧半元件, | zh_TW |
| dc.subject.keyword | SOI, | en |
| dc.relation.page | 42 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2009-06-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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