具聚合物薄膜多層堆疊組件於電子封裝製程之非線性變形研究

Abstract

隨著全球對電子零件的需求提升，市場對於半導體晶片的數量和品質要求也 隨之水漲船高，然而隨著摩爾定律（Moore's law）逐漸達到瓶頸，半導體產業的晶片封裝技術也面臨著挑戰，尤其是在封裝製程中，存在不可避免的溫度梯度分佈，使得在異質材料之間，由於材料彈性模數（Modulus）與熱膨脹係數（Coefficient of thermal expansion）差異引致的熱翹曲變形（Warpage）問題，顯著地影響著晶片製程可靠度與產品性能表現。 於半導體封裝製程中，包含有晶片黏合膠（Die-attach adhesive）、底部填充膠（Underfill）和固態模封材料（Epoxy molding compound），都是晶片封裝技術 常使用具有非線性機械行為的聚合物（Polymer）材料。本文提出以具備時變性 （Time-dependent）和溫變性（Temperature-dependent）的黏彈性材料（Viscoelastic material）模型，分析使用於打線技術（Wire bonding）及球格陣列封裝（Ball grid array）的晶片黏合膠：實驗方面透過拉伸實驗（Tensile test）和流變儀實驗 （Rheometer test），輔以聚合物材料的應力應變曲線（Stress-strain curve）、鬆弛 現象（Relaxation）與主導曲線（Master curve）分析，再運用有限元素法建立模型， 經過和Matlab 演算法的執行與整合，運用其最佳化函式得出最適黏彈性材料的材料參數，以探討溫度變化速率對晶片整體熱翹曲變形的影響。

As global demand for electronic components increases, the market's requirements for the quantity and quality of semiconductor chips are also rising. However, with Moore's Law approaching its limits, the semiconductor industry faces challenges in chip packaging technology. Specifically, the temperature gradient distribution during the packaging process causes thermal warpage deformation due to the mismatch of the elastic modulus and the coefficient of thermal expansion between different materials. This significantly affects the reliability of chip manufacturing and product performance. In semiconductor packaging processes, materials such as die-attach adhesive, underfill, and epoxy molding compounds, which exhibit nonlinear mechanical behavior, are commonly used. This study proposes using a viscoelastic material model with time-dependent and temperature-dependent properties to analyze die-attach adhesive used in wire bonding and ball grid array packaging. Experimentally, tensile and rheometer tests were conducted, supported by stress-strain curve analysis, relaxation test, and master curve analysis of polymer materials. A model was then established using the finite element method, and the optimal viscoelastic material parameters were obtained through execution and integration with Matlab algorithms. This approach aims to explore the impact of temperature change rates on the overall thermal warpage deformation of the chip.