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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | zh_TW |
dc.contributor.advisor | Jenn-Gwo Hwu | en |
dc.contributor.author | 廖威騏 | zh_TW |
dc.contributor.author | Wei-Chi Liao | en |
dc.date.accessioned | 2024-07-12T16:15:09Z | - |
dc.date.available | 2024-07-13 | - |
dc.date.copyright | 2024-07-12 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-07-09 | - |
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Chen, K.-C. Chen, and J.-G. Hwu, “Fringing field induced current coupling in concentric metal–insulator–semiconductor (MIS) tunnel diodes with ultra-thin oxide,” AIP Advances, vol. 12, no. 4, p. 045116, 04 2022. [24] S.-W. Huang and J.-G. Hwu, “Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing,” IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1658–1664, 2003. [25] MOS (metal oxide semiconductor) physics and technology, author=Nicollian, Edward H and Brews, John R. John Wiley & Sons, 2002. [26] Z. Wang, Z. Lin, M. Si, and P. D. Ye, “Characterization of Interface and Bulk Traps in Ultrathin Atomic Layer-Deposited Oxide Semiconductor MOS Capacitors With HfO2/In2O3 Gate Stack by C-V and Conductance Method,” Frontiers in Materials, vol. 9, 2022. [27] C.-Y. Huang and J.-G. Hwu, “Enhanced Photo Sensing and Lowered Power Consumption in Concentric MIS Devices by Monitoring Outer Ring Open-Circuit Voltage With Biased Inner Gate,” IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3417–3423, 2021. [28] Y.-C. Lin and J.-G. Hwu, “Current Polarity Changeable Concentric MIS Tunnel Photodiode With Linear Photodetectivity via Inner Gate Biasing and Outer Ring Short-Circuit Operation,” IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5184–5189, 2023. [29] C. D. Matthus, A. J. Bauer, L. Frey, and T. Erlbacher, “Wavelengthselective 4H-SiC UV-sensor array,” Materials Science in Semiconductor Processing, vol. 90, pp. 205–211, 2019. [Online]. [30] P. K. Chang and J. G. Hwu, “Enhanced irradiance sensitivity of 4H-SiC based ultraviolet sensor introducing laterally gated Al/SiO2/SiC tunnel diode structure with low gate bias,” Journal of Applied Physics, vol. 124, no. 2, p. 024503, 07 2018. [31] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. 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Hwu, “Edge-Etched Al2O3 Dielectric as Charge Storage Region in a Coupled MIS Tunnel Diode Sensor,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 825–833, 2020. [35] R. Ishikawa, M. Hara, H. Tanaka, M. Kaneko, and T. Kimoto, “Electron mobility along 〈0001〉 and 〈1100〉 directions in 4H-SiC over a wide range of donor concentration and temperature,” Applied Physics Express, vol. 14, no. 6, p. 061005, jun 2021. [Online]. [36] Z. Zhang, Z. Wang, Y. Guo, and J. Robertson, “Carbon cluster formation and mobility degradation in 4H-SiC MOSFETs,” Applied Physics Letters, vol. 118, no. 3, p. 031601, 01 2021. [37] R. Engel-Herbert, Y. Hwang, and S. Stemmer, “Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces,” Journal of Applied Physics, vol. 108, no. 12, p. 124101, 12 2010. [38] P. B. Klein, “Carrier lifetime measurement in n 4H-SiC epilayers,” Journal of Applied Physics, vol. 103, no. 3, p. 033702, 02 2008. [39] S. Ichikawa, K. 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Schroder, and T. Mikolajick, “Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells,” in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 26.8.1–26.8.3. [48] M. H. Park, Y. H. Lee, H. J. Kim, Y. J. Kim, T. Moon, K. D. Kim, J. Muller, A. Kersch, U. Schroeder, T. Mikolajick, and C. S. Hwang. [49] E. Yurchuk, J. Muller, J. Paul, T. Schl ¨ osser, D. Martin, R. Hoffmann, ¨ S. Mueller, S. Slesazeck, U. Schr ¨ oeder, R. Boschke, R. van Bentum, ¨ and T. Mikolajick, “Impact of scaling on the performance of hfo2-based ferroelectric field effect transistors,” IEEE Transactions on Electron Devices, vol. 61, no. 11, pp. 3699–3706, 2014. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93008 | - |
dc.description.abstract | 本篇論文重點為探討兩種不同在碳化矽基板上成長氧化層的新穎製程方法,透過材料及電性分析探討氧化層及碳化矽介面處的缺陷密度以及其對於電容-電壓和電流-電壓特性的影響,並探究將金屬/二氧化矽/碳化矽與金屬/氧化鋁/二氧化矽/碳化矽兩種結構的半導體元件分別應用於紫外光感測器以及記憶體之表現。本論文首先介紹一種利用爐管在低於1000 °C的間歇噴濺水合氧化法的創新製程,其在一小時內可成長出約3到7奈米厚的二氧化矽層,並且藉由電導方法得出在平能帶處之介面缺陷密度可低至2 × 10^11 cm^-2eV^-1,與其他前人的研究相比幾乎是最低值。此外,利用此法製造之碳化矽金氧半元件於常溫下偏壓在-6 V,發現其在紫外光照射下之光電流與暗電流相比可高出超過三個數量級,並且在不同功率的紫外光下之光電流展現出高度線性相關性。此元件在從常溫到100 °C高溫下的紫外光感測性能也表現出極佳的可靠度。另一種氧化層製程方法是在常溫下於純水中將碳化矽晶圓透過陽極氧化的技術成長出一層極薄的二氧化矽,再利用熱蒸鍍薄鋁結合陽極氧化的方式形成高介電常數之氧化鋁絕緣層,發現其於平能帶處之介面缺陷密度更可低至1 × 10^11 cm^-2eV^-1。透過氧化鋁層的堆疊,碳化矽金氧半元件的閘極漏電流可在不降低閘極電容的同時被有效的抑制。此外,氧化鋁與二氧化矽介面處的陷阱可做為電荷儲存之用,使得其電容-電壓特性展現出很大的遲滯現象,此特性可做為記憶體之應用。在記憶體的可靠度測試中,發現在100次讀寫操作循環下仍依舊保持穩定的狀態’0’及狀態’1’電容,顯示其具有做為與碳化矽積體電路整合的記憶體元件之潛力。本篇論文於碳化矽氧化層製程方法之研究有突破創新,相信在碳化矽元件的發展及應用上有其重要性。 | zh_TW |
dc.description.abstract | The purpose of this thesis is to investigate two novel fabrication methods for growing oxide layers on a 4H-SiC substrate. The defect density at the SiO2 / 4H-SiC interface, the C-V and the I-V characteristics, and the performance of semiconductor devices with structures of Al/SiO2/4H-SiC and Al/Al2O3/SiO2/4H-SiC, in applications of UV sensors and memory devices are studied. Firstly, this thesis introduces an innovative fabrication process using intermittent spray hydrated oxidation (ISHO) in a furnace at a temperature below 1000 °C, which is capable of growing about 3 nm to 7 nm of SiO2 within one hour. The interface trap density (D_it) at the flat band voltage is found to be as low as 2 × 10^11 cm^-2eV^-1, which is one of the lowest values in the existing literatures. Additionally, the 4H-SiC metal-insulator-semiconductor (MIS) devices fabricated using this method demonstrate outstanding UV sensing capabilities, with demonstrated photocurrent windows extending over three orders of magnitude in amplification and having linear responsivity, as well as maintaining a photo-to-dark current ratio (PDCR) of about two to three orders of magnitude even at high temperatures up to 100 °C. The other process involves growing a thin SiO2 layer on the 4H-SiC wafers through anodic oxidation (ANO) in DI water at room temperature, followed by thermal evaporation of thin aluminum layers and the ANO technique to form high-κ Al2O3 insulating layers. This yields an even lower D_it of 1 × 10^11 cm^-2eV^-1 at the flat band voltage. With stacking of the Al2O3 layer, the gate leakage current in the 4H-SiC MIS devices is effectively suppressed without notably degrading the gate capacitance. Furthermore, the traps at the Al2O3 / SiO2 interface can be utilized for charge storage purposes. These traps result in significant hysteresis phenomenon in the C-V characteristics, which is suitable for memory applications. In the memory endurance test, the capacitances of the state ‘0’ and the state ‘1’ remained stable through 100 read-write cycles operation, demonstrating the potential for integration as embedded memory with silicon carbide ICs. This thesis presents breakthrough innovations in the fabrication of the oxide layer in silicon carbide devices, highlighting its significance in the development and applications of silicon carbide devices. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-12T16:15:09Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-07-12T16:15:09Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xiv Chapter 1 Introduction 1 1-1 Motivation 2 1-2 Properties of 4H-SiC Wide Bandgap Semiconductor 4 1-3 Oxidation Processes and Interface Characterization 5 1-3-1 Thermal Oxidation and Carbon Clustering 5 1-3-2 Anodic Oxidation (ANO) Technique 6 1-3-3 Interface Trap Density Analyses 7 1-4 Photo-sensing Capability of MIS Devices 8 1-5 High-κ Dielectric Stacking and Charge-trapping Effect 9 1-6 Summary 11 Chapter 2 Interface Analyses for SiO2 Grown by Sub-1000 °C Intermittent Spray Hydrated Oxidation (ISHO) and Investigation for UV Sensor Applications 23 2-1 Introduction 24 2-2 Experimental 25 2-3 Results and Discussion 26 2-3-1 Material Characterization of the SiO2 Layer and Deal-Grove Model Fitting for ISHO 26 2-3-2 Electrical Characterization and Interface Trap Density Analysis 27 2-3-3 UV Sensing Capabilities and Temperature-dependent Reliability 30 2-4 Summary 34 Chapter 3 Low Interface Trap Density 4H-SiC MIS Structure with Al2O3 Stacking on Thin SiO2 for Low Thermal Budget Embedded Memory Applications 55 3-1 Introduction 56 3-2 Experimental 56 3-3 Results and Discussion 58 3-3-1 Material and Electrical Characterization of the Devices with M(AO)2IS, M(AO)IS, and M(AO)S Structures 58 3-3-2 Interface Property Analysis of Al2O3-stacking MIS Devices w/ & w/o SiO2 Interfacial Layer By TCAD Simulation 60 3-3-3 Investigation of Memory Applications 63 3-4 Summary 64 Chapter 4 Conclusion and Future Work 81 4-1 Conclusion 82 4-2 Future Work 84 4-2-1 Parameters Optimization and Mechanism Study for ISHO 84 4-2-2 ANO Under UV Illumination 85 4-2-3 High-κ Stacking with HfO2 86 References 90 | - |
dc.language.iso | en | - |
dc.title | 碳化矽金氧半結構氧化層製程開發及元件應用之研究 | zh_TW |
dc.title | Oxidation Process Development and Device Applications in 4H-SiC MIS Structure | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 林浩雄;陳奕君 | zh_TW |
dc.contributor.oralexamcommittee | Hao-Hsiung Lin;I-Chun Cheng | en |
dc.subject.keyword | 碳化矽,金氧半元件,氧化層成長,介面缺陷密度,紫外光感測器,氧化鋁堆疊,記憶體, | zh_TW |
dc.subject.keyword | 4H-SiC,Metal-insulator-semiconductor (MIS),Oxidation processes,Interface trap density,UV sensor,Al2O3 stacking,Memory, | en |
dc.relation.page | 98 | - |
dc.identifier.doi | 10.6342/NTU202401607 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2024-07-09 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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