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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92656| 標題: | 高效率脈衝式極化傳輸機與低複雜度預失真 A Highly Efficient Pulse-Modulated Polar Transmitter with Low-Complexity Digital Predistortion |
| 作者: | 徐碩亨 Shuo-Heng Xu |
| 指導教授: | 陳昭宏 Jau-Horng Chen |
| 關鍵字: | 功率放大器,極化座標發射機,數位脈衝調變,等化濾波器,數位預失真, Power amplifiers (PAs),Polar transmitters,Digital pulse-width modulation (DPWM),Equalization filter,Digital predistortion (DPD), |
| 出版年 : | 2024 |
| 學位: | 博士 |
| 摘要: | 本論文提出了一種採用新的數位脈衝寬度調變技術下的新型發射機架構和與之搭配的數位預失真方案。在第五代行動通訊系統的廣泛應用需求,使得對於高速率數據和低延遲的傳輸提出了更高的要求。為了滿足這些嚴峻的需求,傳輸信號的峰對均值功率比在採用複雜的先進調變技術後也因此提高。在以滿足線性度規範運作傳輸機時,增加峰對均值功率比的調變信號往往有降低了發射機效率的疑慮。因此,開發一種能夠平衡效率和線性度需求的發射機對於新世代通訊的傳輸機有其必要性。
論文的第一部分首先應用了一種數位結合方法,用於調變出能與現代通訊系統相容的多階級脈衝寬度調變信號。使用這種方法,傳輸機系統對被動射頻元件不匹配的依賴性降低。理論模擬上,由脈衝寬度調變引起的諧波可以完全消除。更進一步的,這種方法在論文中用於驅動商業用的Doherty功率放大器。結合多階級脈衝式調變之極化發射機與業界廣為採用的高效率功率放大器架構,可以實現效率和線性度的兼顧。在論文中進一步分析應用具有交錯技術的典型脈衝式調變之極化發射機和數位結合方法兩者技術的差異。第一部分透過實驗驗證多階級脈衝式調變之極化發射機和提出的數位結合方法作為結尾。這種方法可以滿足線性度的要求,而無需進一步添加資源。 論文的第二部分接著專注在緩解功率放大器在傳輸寬頻信號時,其所採用的預失真方案資源需求。透過分析影響基地台傳輸機的非線性因素,研究指出在對功率放大器進行建模以實施線性化技術於寬頻訊號應用時,記憶效應是主要的挑戰。在論文的第二部分中,首先採用了論文第一部分提出的多階級脈衝式調變訊號抑制了長期記憶效應。針對短期記憶效應,採用了兩個記憶深度的記憶模型。與傳統的I/Q調變發射機相比,線性化過程可以使用更少的資源來實現。 延續第二部分的概念,一種新的替代預失真方法在第三部分被提出,以達成在寬頻傳輸下低資源需求在的應用。論文的第三部分應對短期記憶效應,提出了使用等化濾波器用於補償寬頻脈衝式調變極化之發射機的動態頻率響應。與經典脈衝式調變極化之發射機模型相比,提出了寬頻脈衝調變式極化之發射機模型並加以驗證。當射頻電路硬體滿足脈衝式調變極化之發射機的操作要求時,該架構中的線性度性能可以達到與複雜的通用記憶多項式模型相當的結果,同時顯著減少了資源。 本文提出的方法適合軟體定義無線電的開發,低使用資源與高效的數位預失真解決方案有潛力促進經濟高效的第五代通訊基地台的推進和建立。 This thesis presents new methods for transmitter architecture and digital predistortion scheme (DPD) based on digital pulse-width modulation (DPWM). With the continuous challenges posed by the fifth-generation (5G) communication system development, it demands more on low latency and high data rates transmission. The advanced modulation signal with an increased peak-to-average power ratio (PAPR) decreases the efficiency of the transmitter when simultaneously addressing linearity demands. Therefore, it is necessary to develop a transmitter that balances efficiency and linearity requirements. The first part of the thesis proposes a digital combining method to modulate multi-level pulse-width signals, which can be compatible with modern communication generation. With this method, the transmitter suffers less from passive radio frequency (RF) component mismatch. Ideally, the harmonics induced by pulse-width modulation (PWM) can be eliminated completely. Furthermore, this method is used to drive the commercially available Doherty power amplifier (DPA). Combining the currently popular high-efficiency power amplifier (PA) architecture and multilevel pulse-modulated polar transmitter (PMPT), this work can maintain efficiency and linearity concurrently. Further, in the text, classical PMPT with interleaving technique and the proposed method are explained and analyzed. The operating principle of multilevel PMPT is discussed and validated on the testbed. This method can meet the linearity requirement without additional resources. The second part of the thesis focuses on alleviating the resource demands of the DPD scheme, which is applied to PA to ensure linearity when transmitting broadband signals. The reason for nonlinearities and the challenge of linearization are analyzed. When implementing linearization techniques, the memory effect emerges as the primary obstacle in modeling the behavior of the PA in wideband applications. The long-term memory effect can be inhibited by the method proposed in the first part of the thesis. A two-tap robust memory DPD model is adopted to target the short-term memory effect. Compared to conventional In-phase/Quadrature (I/Q) transmitters, the linearization process can use fewer resources. Building on the concept introduced in the second part, an alternative method is further presented to address low resource requirements. Targeting the short-term memory effect, an equalization filter is proposed to compensate for the dynamic frequency response with wideband PMPT. Compared with the classical PMPT mathematical model, the broadband PMPT model is proposed and validated. With the hardware meeting the operational prerequisites of PMPT, this architecture achieves comparable linearity performance to employing a complex general memory polynomial model (GMP) for the linearization process while significantly reducing resource demands. The approach presented in this thesis is applicable to the development of software-defined radio, and the resource-efficient DPD solution can potentially facilitate the advancement and establishment of cost-effective 5G base stations. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92656 |
| DOI: | 10.6342/NTU202401016 |
| 全文授權: | 未授權 |
| 顯示於系所單位: | 工程科學及海洋工程學系 |
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| ntu-112-2.pdf 未授權公開取用 | 4.7 MB | Adobe PDF |
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