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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92556完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 許朝硯 | zh_TW |
| dc.contributor.author | Chao-Yen Hsu | en |
| dc.date.accessioned | 2024-04-12T16:13:58Z | - |
| dc.date.available | 2024-04-13 | - |
| dc.date.copyright | 2024-04-12 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-04-11 | - |
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[2] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A 1gs/s, 12 b, singlechannel pipelined adc with deadzonedegenerated ring amplifiers,” IEEE Journal of SolidState Circuits , vol. 54, pp. 646–658, Mar. 2019. [3] B. Razavi, Principles of Data Conversion System Design. WileyIEEE Press, first ed., 1995. [4] W. Jiang, Y. Zhu, M. Zhang, C.H. Chan, and R. P. Martins, “A temperature stabilized singlechannel 1gs/s 60db sndr sarassisted pipelined adc with dynamic gmrbased amplifier,” IEEE Journal of SolidState Circuits , vol. 55, pp. 322–332, Feb. 2020. [5] C.Y. Lin, Y.H. Wei, and T.C. Lee, “27.7 a 10b 2.6gs/s timeinterleaved sar adc with background timingskew calibration,” in 2016 IEEE International SolidState Circuits Conference (ISSCC), pp. 468–469, Jan. 2016. [6] J.W. Nam, M. Hassanpourghadi, A. Zhang, and M. S.W. Chen, “A 12bit 1.6, 3.2, and 6.4 gs/s 4b/cycle timeinterleaved sar adc with dual reference shifting and inter polation,” IEEE Journal of SolidState Circuits , vol. 53, pp. 1765–1779, Jun. 2018. [7] D. Cline and P. Gray, “A power optimized 13b 5 msamples/s pipelined analog todigital converter in 1.2 /spl mu/m cmos,” IEEE Journal of SolidState Circuits , vol. 31, pp. 294–303, Mar. 1996. [8] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.K. Moon, “Ring amplifiers for switched capacitor circuits,” IEEE Journal of SolidState Cir cuits, vol. 47, pp. 2928–2942, Dec. 2012. [9] Y. Lim and M. P. Flynn, “A 100 ms/s, 10.5 bit, 2.46 mw comparatorless pipeline adc using selfbiased ring amplifiers,” IEEE Journal of SolidState Circuits , vol. 50, pp. 2331–2341, Oct. 2015. [10] K. M. Megawer, F. A. Hussien, M. M. Aboudina, and A. N. Mohieldin, “A system atic design methodology for classabstyle ring amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, pp. 1169–1173, Sep. 2018. [11] D. J. Tony Carusone and K. Martin, Analog Integrated Circuit Design. Wiley, sec ond ed., 2012. [12] Y. Lim and M. P. Flynn, “A calibrationfree 2.3 mw 73.2 db sndr 15b 100 ms/s fourstage fully differential ring amplifier based sarassisted pipeline adc,” in 2017 Symposium on VLSI Circuits, pp. C98–C99, Jun. 2017. [13] T.C. Hung, J.C. Wang, and T.H. Kuo, “16.4 a calibrationfree 71.7db sndr 100ms/s 0.7mw weightedaveraging correlated level shifting pipelined sar adc with speed enhancement scheme,” in 2020 IEEE International SolidState Circuits Conference (ISSCC) , pp. 256–258, Feb. 2020. [14] J.C. Wang and T.H. Kuo, “A 72db sndr 130ms/s 0.8mw pipelinedsar adc using a distributed averaging correlated level shifting ring amplifier,” IEEE Journal of SolidState Circuits , vol. 57, pp. 3794–3803, Dec. 2022. [15] C. Y. Lee, P. K. Venkatachala, A. ElShater, B. Xiao, H. Hu, and U.K. Moon, “Cas coded ring amplifiers for high speed and high accuracy settling,” in 2019 IEEE In ternational Symposium on Circuits and Systems (ISCAS), pp. 1–5, May 2019. [16] P. K. Venkatachala, S. Leuenberger, A. ElShater, C. Lee, Y. Xu, B. Xiao, M. Oat man, and U.K. Moon, “Process invariant biasing of ring amplifiers using deadzone regulation circuit,” in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, May 2018. [17] J. Xavier, P. Barquinha, and J. Goes, “Design of a ringamplifier robust against pvt variations in deepnanoscale finfet cmos,” in 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS), pp. 1–5, Nov. 2021. [18] M. Zhan, L. Jie, X. Tang, and N. Sun, “A 0.004mm2 200ms/s pipelined sar adc with kt/c noise cancellation and robust ringamp,” in 2022 IEEE International SolidState Circuits Conference (ISSCC), vol. 65, pp. 164–166, Feb. 2022. [19] Y. Chen, J. Wang, H. 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Martins, “An auxiliarychannelsharing background distortion and gain calibration achieving >8db sfdr improvement over 4th nyquist zone in 1gs/s adc,” in 2021 Symposium on VLSI Circuits, pp. 1–2, Jun. 2021. [24] M. Gu, Y. Zhong, L. Jie, and N. Sun, “A 12b 1gs/s pipelined adc with digital back ground calibration of interstage gain, capacitor mismatch, and kickback errors,” in ESSCIRC 2023IEEE 49th European Solid State Circuits Conference (ESSCIRC) , pp. 329–332, Sep. 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92556 | - |
| dc.description.abstract | 本論文提出了一種結合動態偏壓和增益提升技術的巢狀環形放大器。所提出之新型放大器在提升增益至近90分貝的同時，保留了環形放大器原本的高迴轉率特性，該架構有助於改善速度與解析度間的設計權衡。此放大器被應用在一個無需校準的十一位元十億取樣頻率單通道管線式線類比數位轉換器系統。與此同時，我們也提出相對應的偏壓電路來緩解環形放大器容易受製程、電壓和溫度變異影響的缺點。
此類比數位轉換器利用28奈米技術製造，在十億赫茲的取樣頻率下，可測得53.52分貝的訊號對雜訊失真比，同時僅耗能14.7毫瓦，量測供應電壓為1伏特，並且達到了159分貝的Schreier效能指標。 | zh_TW |
| dc.description.abstract | In this thesis, we propose a nested ring amplifier that combines dynamic bias and gain-boost techniques. The proposed amplifier significantly enhances gain, achieving nearly 90 dB, while retaining the high-slew capability inherent in ring amplifiers. This enhancement relaxes speed and resolution constraints. The amplifier is implemented in a calibration-free 11-bit 1GS/s single-channel pipelined ADC. Furthermore, the proposed biasing circuits are used to alleviate the process, voltage, and temperature (PVT) -sensitive issues associated with ring amplifiers.
Fabricated in a 28-nm CMOS technology, the ADC achieves 53.52-dB SNDR under sampling rate of 1GS/s, consuming 14.7 mW from a 1-V supply and yielding a Schreier figure-of-merit (FoMs) of 159 dB. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-04-12T16:13:58Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-04-12T16:13:58Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Contents
誌謝 iii 摘要 v Abstract vi Contents vii List of Figures x List of Tables xiii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Fundamentals 3 2.1 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . 5 2.2.2 Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . 5 2.2.3 SignaltoNoise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . 6 2.2.4 SignaltoNoise and Distortion Ratio (SNDR) . . . . . . . . . . . 6 2.2.5 Effective Number of Bits (ENOB) . . . . . . . . . . . . . . . . . 6 2.2.6 SpuriousFree Dynamic Range (SFDR) . . . . . . . . . . . . . . 6 2.2.7 Total Harmonic Distortion (THD) . . . . . . . . . . . . . . . . . 7 2.2.8 Dynamic Range (DR) . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.9 Figure of Merit (FoM) . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Ring amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.3 Steady State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 System Architecture and Implementation 14 3.1 1.5bit/stage vs 2.5bit/stage . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Multiplying DAC . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 3bit Flash Backend Circuit . . . . . . . . . . . . . . . . . . . . 20 3.3 Nested Ring Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.2 Proposed Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 PVT Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.4 Proposed Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.5 CMFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 Peripheral Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 Bootstrapped Switch . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.4 Synchronization, Decimation and Output Buffer . . . . . . . . . 32 3.5 Layout Floor Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6.1 Chip 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6.2 Chip 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 Measurement Result 39 4.1 Chip Micrograph and Printed Circuit Board . . . . . . . . . . . . . . . . 39 4.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.1 Basic Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.2 Temperature Chamber . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.3 Phase Unbalance . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.1 Chip 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.2 Chip 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Conclusion 52 5.1 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bibliography 54 | - |
| dc.language.iso | en | - |
| dc.subject | 無須校準 | zh_TW |
| dc.subject | 管線式類比數位轉換器 | zh_TW |
| dc.subject | 增益提升 | zh_TW |
| dc.subject | 動態偏壓 | zh_TW |
| dc.subject | 環形放大器 | zh_TW |
| dc.subject | ring amplifier | en |
| dc.subject | dynamic bias | en |
| dc.subject | gain boost | en |
| dc.subject | calibration-free | en |
| dc.subject | Pipelined ADC | en |
| dc.title | 具有製程電壓溫度不敏感性巢狀環形放大器之十一位元十億赫茲管線式類比數位轉換器 | zh_TW |
| dc.title | A 11b 1GS/s Pipelined ADC with PVT-insensitive Nested Ring Amplifiers | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林宗賢;陳信樹;鍾勇輝 | zh_TW |
| dc.contributor.oralexamcommittee | Tsung-Hsien Lin;Hsin-Shu Chen;Yung-Hui Chung | en |
| dc.subject.keyword | 管線式類比數位轉換器,無須校準,環形放大器,動態偏壓,增益提升, | zh_TW |
| dc.subject.keyword | Pipelined ADC,calibration-free,ring amplifier,dynamic bias,gain boost, | en |
| dc.relation.page | 57 | - |
| dc.identifier.doi | 10.6342/NTU202400852 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-04-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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