基於FPGA的全同態加密軟硬體共同設計架構

Abstract

在現今社會，隱私變得日益重要。歐盟提出的《通用數據保護條例》（GDPR）規定了數據收集和保護的規則，造成許多組織或個人在資料的取得與使用上構成了挑戰。雖然目前有許多種隱私保護的技術，但全同態加密（FHE）以其在數學上的高度安全性脫穎而出。FHE能讓資料在加密的情況下進行計算而無需解密。然而，與非加密計算相比，它帶來了額外的計算開銷。

在本論文中，我們提出了一種專為FPGA定制的軟硬體共同設計方法，以進一步提高全同態加密計算的性能。該方法包括負責運行硬體的後端和用於生成特定應用硬體配置的自動化前端。FHE硬體設計包括配置多個計算單元，以及排程和執行微指令於特製的硬體上。自動化前端探索各個不同排列組合的計算單元，去找到最佳的硬體配置。實驗結果顯示了提出方法在不同應用中的有效性和其加速效果。

In the digital age, privacy is increasingly important. The General Data Protection Regulation (GDPR) lays out rules for how data is collected and protected, posing challenges for many organizations. While there are several techniques to preserve privacy, fully homomorphic encryption (FHE) stands out as the most mathematically secure. FHE permits evaluations on data that is encrypted without requiring decryption. However, it introduces significant computational overhead compared to non-encrypted computations.

In this thesis, we introduce a hardware/software co-design methodology specifically crafted for FPGA to improve the performance of fully homomorphic encryption. The methodology encompasses a hardware backend responsible for running the hardware and an automated frontend employed to generate application-specific hardware configurations. The hardware design incorporates multiple functional units for efficient homomorphic operations, complemented by a customized microinstruction scheduling algorithm. The automated frontend engages in design space exploration to pinpoint Pareto-optimal synthesis configurations. The results show the effectiveness of the methodology across different applications.