請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92481完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 洪士灝 | zh_TW |
| dc.contributor.advisor | Shih-Hao Hung | en |
| dc.contributor.author | 施承志 | zh_TW |
| dc.contributor.author | Cheng-Jhih Shih | en |
| dc.date.accessioned | 2024-03-26T16:15:05Z | - |
| dc.date.available | 2024-03-27 | - |
| dc.date.copyright | 2024-03-26 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2023-11-28 | - |
| dc.identifier.citation | [1] Alveo u280 data center accelerator card specifications. Online: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html# specifications.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92481 | - |
| dc.description.abstract | 在現今社會，隱私變得日益重要。歐盟提出的《通用數據保護條例》（GDPR）規定了數據收集和保護的規則，造成許多組織或個人在資料的取得與使用上構成了挑戰。雖然目前有許多種隱私保護的技術，但全同態加密（FHE）以其在數學上的高度安全性脫穎而出。FHE能讓資料在加密的情況下進行計算而無需解密。然而，與非加密計算相比，它帶來了額外的計算開銷。
在本論文中，我們提出了一種專為FPGA定制的軟硬體共同設計方法，以進一步提高全同態加密計算的性能。該方法包括負責運行硬體的後端和用於生成特定應用硬體配置的自動化前端。FHE硬體設計包括配置多個計算單元，以及排程和執行微指令於特製的硬體上。自動化前端探索各個不同排列組合的計算單元，去找到最佳的硬體配置。實驗結果顯示了提出方法在不同應用中的有效性和其加速效果。 | zh_TW |
| dc.description.abstract | In the digital age, privacy is increasingly important. The General Data Protection Regulation (GDPR) lays out rules for how data is collected and protected, posing challenges for many organizations. While there are several techniques to preserve privacy, fully homomorphic encryption (FHE) stands out as the most mathematically secure. FHE permits evaluations on data that is encrypted without requiring decryption. However, it introduces significant computational overhead compared to non-encrypted computations.
In this thesis, we introduce a hardware/software co-design methodology specifically crafted for FPGA to improve the performance of fully homomorphic encryption. The methodology encompasses a hardware backend responsible for running the hardware and an automated frontend employed to generate application-specific hardware configurations. The hardware design incorporates multiple functional units for efficient homomorphic operations, complemented by a customized microinstruction scheduling algorithm. The automated frontend engages in design space exploration to pinpoint Pareto-optimal synthesis configurations. The results show the effectiveness of the methodology across different applications. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-03-26T16:15:05Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-03-26T16:15:05Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Verification Letter from the Oral Examination Committee i
Acknowledgements iii 摘要 v Abstract vii Contents ix List of Figures xi List of Tables xiii Chapter 1 Introduction to Privacy Preserving Techniques 1 1.1 Local Computation 2 1.2 Trusted Execution Environment (TEE) 3 1.3 Differential Privacy (DP) 5 1.4 Multi Party Computation (MPC) 7 1.5 Fully Homomorphic Encryption (FHE) 8 Chapter 2 Related Work 11 2.1 History of Fully Homomorphic Encryption 11 2.2 CKKS Scheme Introduction 13 2.3 FHE Applications and Compilers 17 2.4 Hardware Accelerators for Fully Homomorphic Encryption 18 2.4.1 ASIC Accelerators 18 2.4.2 FPGA Accelerators 19 2.4.3 Accelerating FHE on GPU 19 Chapter 3 Methodology 21 3.1 Hardware Design Space 23 3.2 HE Microinstruction Scheduler 26 3.3 Automated Hardware/Software Co-Design 27 Chapter 4 Evaluation 31 4.1 Experimental Setup 31 4.2 Synthesis of FHE Accelerators 32 4.3 Effects of HE Microinstruction Scheduling 34 4.4 Design Space Exploration 35 Chapter 5 Conclusion and Future Work 41 References 43 | - |
| dc.language.iso | en | - |
| dc.subject | 軟硬體共同設計 | zh_TW |
| dc.subject | 可程式化邏輯閘陣列 | zh_TW |
| dc.subject | 高效能計算 | zh_TW |
| dc.subject | 全同態加密 | zh_TW |
| dc.subject | Fully Homomorphic Encryption | en |
| dc.subject | Hardware/Software Co-Design | en |
| dc.subject | FPGA | en |
| dc.subject | High-performance computing | en |
| dc.title | 基於FPGA的全同態加密軟硬體共同設計架構 | zh_TW |
| dc.title | A Hardware/Software Co-Design Framework for FPGA-based Fully Homomorphic Encryption | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 施吉昇;涂嘉恆;彭啟峰 | zh_TW |
| dc.contributor.oralexamcommittee | Chi-Sheng Shih;Chia-Heng Tu;Chi-Feng Peng | en |
| dc.subject.keyword | 高效能計算,可程式化邏輯閘陣列,全同態加密,軟硬體共同設計, | zh_TW |
| dc.subject.keyword | High-performance computing,FPGA,Fully Homomorphic Encryption,Hardware/Software Co-Design, | en |
| dc.relation.page | 51 | - |
| dc.identifier.doi | 10.6342/NTU202304453 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2023-11-29 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 資訊工程學系 | - |
| dc.date.embargo-lift | 2025-06-30 | - |
| 顯示於系所單位： | 資訊工程學系 | |
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