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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王暉 | zh_TW |
| dc.contributor.advisor | Huei Wang | en |
| dc.contributor.author | 錢俊嘉 | zh_TW |
| dc.contributor.author | Chun-Chia Chien | en |
| dc.date.accessioned | 2024-01-26T16:23:16Z | - |
| dc.date.available | 2024-01-27 | - |
| dc.date.copyright | 2024-01-26 | - |
| dc.date.issued | 2023 | - |
| dc.date.submitted | 2024-01-04 | - |
| dc.identifier.citation | [1] ITU-R website [Online] https://www.itu.int/en/Pages/default.aspx
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Malignaggi, "A V-Band Miniaturized Bidirectional Switchless PALNA in SiGe:C BiCMOS Technology," in IEEE Microwave and Wireless Components Letters, vol. 30, no. 8, pp. 786-789, Aug. 2020. [37] A. A. Nawaz, J. D. Albrecht and A. Çağrı Ulusoy, "A 28-/60-GHz Band-Switchable Bidirectional Amplifier for Reconfigurable mm-Wave Transceivers," in IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 7, pp. 3197-3205, July 2020. [38] A. Ergintav, F. Herzel, J. Borngräber, D. Kissinger and H. J. Ng, "An integrated 122GHz differential frequency doubler with 37GHz bandwidth in 130 nm SiGe BiCMOS technology," 2017 IEEE MTT-S International Conference on Microwaves for Intelligent Mobility (ICMIM), Nagoya, Japan, 2017, pp. 53-56 [39] H. -H. Hsieh and L. -H. Lu, "A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-μm CMOS," in IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 8, pp. 1895-1902, Aug. 2009. [40] G. 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Wu et al., "A Compact W-Band Power Amplifier with a Peak PAE of 21.1% in 65-nm CMOS Technology," in IEEE Microwave and Wireless Technology Letters, vol. 33, no. 6, pp. 703-706, June 2023. [50] C. -W. Wu, Y. -H. Lin, Y. -H. Hsiao, C. -F. Chou, Y. -C. Wu and H. Wang, "Design of a 60-GHz High-Output Power Stacked- FET Power Amplifier Using Transformer-Based Voltage-Type Power Combining in 65-nm CMOS," in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 10, pp. 4595-4607, Oct. 2018. [51] S. C. Cripps, RF Power Amplifiers for wireless Communication. Bostom, MA: Artech House, 2000. [52] C. Cheng, "Neutralization and Unilateralization," in IRE Transactions on Circuit Theory, vol. 2, no. 2, pp. 138-145, June 1955. [53] Deferm, Noël, and Patrick Reynaert. CMOS Front Ends for Millimeter-Wave Wireless Communication Systems. KU Leuven, 2015. [54] H. Nishiyama and M. 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Huang, "A CMOS W-band ×4 frequency multiplier with cascading push-pull frequency doublers," 2012 Asia Pacific Microwave Conference Proceedings, Kaohsiung, Taiwan, 2012, pp. 166-168. [59] K. W. J. Chew et al., "RF performance of 28nm PolySiON and HKMG CMOS devices," 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, AZ, USA, 2015, pp. 43-46. [60] Microwaves101 website [online]: https://www.microwaves101.com/encyclopedia/ noise-parameter-extraction-using-source-pull [61] Y. -H. Yu, W. -H. Hsu and Y. -J. E. Chen, "A Ka-Band Low Noise Amplifier Using Forward Combining Technique," in IEEE Microwave and Wireless Components Letters, vol. 20, no. 12, pp. 672-674, Dec. 2010. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91411 | - |
| dc.description.abstract | 在這本論文由以下三個部分組成，一個D頻段低功耗高轉換增益之倍頻器和一個Ka頻段低雜訊放大器與W頻段雙向功率低雜訊放大器的設計與量測結果。
首先是預計作為D頻段訊號源之倍頻器，使用的製程為28奈米金氧半場效電晶體，此倍頻器使用馬遜平衡器來產生180°相位差之訊號，並透過選擇偏壓點在Class-B 使電路有最多的諧波項，最高的轉換增益可達-4.5 dB，而輸出3dB頻寬從126-146 GHz，達到15% 的比例頻寬。 第二部分提出應用於Ka頻段接收機中之低功耗低雜訊放大器，使用的製程為90奈米金氧半場效電晶體。此電路使用雙重變壓器耦合與電流共用技術與在第一級提供足供增益及低雜訊之表現，而在第二級使用本人所提出消除寄生效應之雙重變壓器耦合進而去提高整體電路的表現。量測結果顯示此顆低雜訊放大器具有18 GHz 之頻寬以及19.7 dB 的增益，並且在30 GHz只有3.2 dB的雜訊指數 最後提出的是設計於W 頻段的雙向功率低雜訊放大器並且比較了有以開關作為切換模態的方式與基於變壓器架構之無開關兩者之間的優劣。無開關功率低雜訊放大器(Switchless bidirectional PA-LNA)，使用選擇電晶體大小與匹配電路使其在OFF 模態時有開路之效果，此時變壓器耦合的匹配電路就有虛擬開關(Virtual Switch)之效果。以此方式設計電路可以同時保有低雜訊放大器與功率放大器之效果，並且可以省去不少的面積。此無開關之功率低雜訊放大器在低雜訊放大器模式有18.5 dB的小訊號增益、21 GHz的3-dB頻寬以及在81 GHz有7 dB的最小雜訊指數，然而在功率放大器的模式則有17.2 dB的小訊號增益和飽和輸出功率則有 10 dBm和9.1% 最高功率附加效率的表現。而在有開關的版本中，在輸出與輸入端使用單刀雙擲開關(SPDT switch)去使得訊號在OFF模態時能有更開路之效果，相對的則會有switch的損耗需要考慮。此有開關之功率低雜訊放大器在低雜訊放大器模式有18.6 dB的小訊號增益、25 GHz 的3-dB頻寬以及在81 GHz 有7.1 dB的最小雜訊指數，然而在功率放大器的模式則有18.2 dB的小訊號增益和則飽和輸出功率有 10 dBm和9 %最大附加效率的表現。 | zh_TW |
| dc.description.abstract | This paper comprises three main sections: the design and measurement results of a low-power, high-conversion-gain D-Band frequency multiplier, a low-noise amplifier (LNA) for the Ka-Band, and a bidirectional low-noise amplifier tailored for the W-Band.
The first section focuses on the D-Band frequency multiplier intended to serve as a signal source. It is fabricated using a 28-nanometer CMOS process and utilizes a Marchand-Balun to generate signals with a 180° phase difference. By optimizing the bias point in Class-B, this circuit achieves a peak conversion gain of -4.5 dB. It provides a 3dB output power bandwidth ranging from 126 to 146 GHz, achieving a 15% fractional bandwidth. The second part introduces a low-power LNA designed for the Ka-Band receiver, fabricated using a 90-nanometer CMOS process. This circuit employs dual transformer coupling and current-sharing techniques in the first stage to deliver ample gain and low-noise performance. In the second stage, a novel dual transformer coupling approach, designed to mitigate parasitic effects, enhances the overall circuit''s performance. Measurement results reveal that this LNA offers an 18 GHz 3-dB bandwidth, a gain of 19.7 dB, and a noise figure of only 3.2 dB at 30 GHz. The final section presents the design of a bidirectional low-noise amplifier for the W-Band and compares two modes: a switchless bidirectional PA-LNA and a switch-based design using transformer configurations. The switchless design achieves an open circuit effect in OFF mode by selecting transistor sizes and matching circuits. This approach emulates a virtual switch within the transformer-coupled matching network. This design enables the circuit to simultaneously function as a low-noise amplifier and a power amplifier while conserving space. In the switchless version, the low-noise amplifier mode provides an 18.5 dB small-signal gain, a 21 GHz 3-dB bandwidth, and a minimum noise figure of 7 dB at 81 GHz. In power amplifier mode, it achieves 17.2 dB small-signal gain, a saturated output power (Psat) of 10 dBm, and a 9.1% peak power-added efficiency (PAEMAX). In the switch version, single-pole double-throw (SPDT) switches at the input and output create open circuits in OFF mode, though there are switch-related losses to consider. In this configuration, the low-noise amplifier mode offers an 18.6 dB small-signal gain, a 25 GHz 3-dB bandwidth, and a minimum noise figure of 7.1 dB at 81 GHz. In power amplifier mode, it provides an 18.2 dB small-signal gain, a saturated output power (Psat) of 10 dBm, a 9% peak power-added efficiency (PAEMAX). | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-01-26T16:23:16Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-01-26T16:23:16Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 ii
中文摘要 iv ABSTRACT vi CONTENTS viii LIST OF FIGURES xi LIST OF TABLES xxii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 4 1.2.1 D-Band Frequency Multiplier in CMOS Process 5 1.2.2 Ka-band LNA in CMOS Process 7 1.2.3 W-Band Bidirectional PA-LNA in CMOS Process 10 1.3 Contributions 12 1.3.1 D-band Frequency Multiplier in CMOS process 12 1.3.2 Ka-band LNA in CMOS Process 13 1.3.3 W-Band Bidirectional PA-LNA in CMOS Process 13 1.4 Thesis Organization 15 Chapter 2 Design of a D-Band Frequency Doubler with gm-Boosting Cascode Topology in 28-nm CMOS 16 2.1 Design Procedure of the D-Band Doubler 16 2.1.1 Device Size and Bias Selection 16 2.1.2 Cascode Configuration Design 21 2.1.3 gm-Boosting Technique 22 2.1.4 Marchand Balun Design 27 2.1.5 Overall Circuit Schematic 30 2.2 Simulation Result and Post-layout 31 2.3 Measurement Result 34 2.4 Trouble Shooting and Discussions 37 2.5 Summary 45 Chapter 3 Ka-Band Low Power Wideband LNA in 90-nm CMOS Process 47 3.1 Introduction 47 3.2 The Design of Ka-band LNA 50 3.2.1 Biasing Selection and Device Selection 50 3.2.2 Current-Reused Double-Transformer-Coupler [44][45]. 57 3.2.3 Concept of New Type Double-Transformer-Coupling 63 3.2.4 Complete Ka-band LNA Schematic 70 3.3 Simulation Result and Post-layout 71 3.4 Experimental Results 76 3.5 Summary 85 Chapter 4 W-Band Bidirectional PA-LNA in 65-nm CMOS Process for Beamformer Application 87 4.1 Phased-Array System[15] 88 4.2 Design Concepts of PA-LNA 90 4.2.1 Amplifier Structure of PA-LNA cores 90 4.3 Design Procedure of the W-Band Bidirectional PA-LNA 93 4.3.1 Bidirectional Matching Network 93 4.3.2 PA-LNA Design Flows 94 4.3.3 Block Diagram of PA 97 4.3.4 Device and Bias Selection 97 4.3.5 Driver Stage Design 101 4.3.6 Input Stage Design 102 4.3.7 Neutralization Capacitive Technique[52] 103 4.3.8 Matching Network 106 4.3.9 Circuit Schematic and OFF-state Impedance Check 111 4.3.10 Design of LNA 115 4.3.11 OFF-state Impedance Check 119 4.3.12 Complete Schematic of Switchless Bidirectional PA-LNA 122 4.3.13 Simulation Result and Post-layout 124 4.3.14 Experimental Result of the Bidirectional PA-LNA 130 4.4 Design of the W-Band bidirectional PA-LNA with switch 138 4.4.1 Circuit Design 138 4.4.2 Switch Bidirectional PA-LNA Simulated Result 144 4.4.3 Experimental Result of the Switch Bidirectional PA-LNA 150 4.5 Trouble Shooting and Discussions 157 4.6 Summary 167 Chapter 5 Conclusions 169 REFERENCE 171 | - |
| dc.language.iso | en | - |
| dc.subject | 寬頻放大器 | zh_TW |
| dc.subject | D頻段 | zh_TW |
| dc.subject | W頻段 | zh_TW |
| dc.subject | 單刀雙擲開關 | zh_TW |
| dc.subject | Ka頻段 | zh_TW |
| dc.subject | 雙向放大器 | zh_TW |
| dc.subject | 無開關雙向放大器 | zh_TW |
| dc.subject | 低雜訊放大器 | zh_TW |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | 互補式金氧半導體 | zh_TW |
| dc.subject | 變壓器匹配網路 | zh_TW |
| dc.subject | low noise amplifier | en |
| dc.subject | switchless bidirectional amplifier | en |
| dc.subject | Ka band | en |
| dc.subject | SPDT | en |
| dc.subject | W band | en |
| dc.subject | D band | en |
| dc.subject | power amplifier | en |
| dc.subject | transformer | en |
| dc.subject | wideband amplifier | en |
| dc.subject | CMOS | en |
| dc.title | 應用於D頻段之倍頻器、5G通訊之低雜訊放大器及應用於次世代相控陣列雙向放大器之設計 | zh_TW |
| dc.title | Design of D-band Frequency Doubler, Low-Noise Amplifiers for 5G Communication and Bidirectional Amplifier for Next-Generation Phased-Arrays | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 王雲杉;黃天偉;蔡政翰;林坤佑 | zh_TW |
| dc.contributor.oralexamcommittee | Yunshan Wang;Tian-Wei Huang;Jeng-Han Tsai;Kun-You Lin | en |
| dc.subject.keyword | 互補式金氧半導體,寬頻放大器,變壓器匹配網路,功率放大器,低雜訊放大器,無開關雙向放大器,雙向放大器,Ka頻段,單刀雙擲開關,W頻段,D頻段, | zh_TW |
| dc.subject.keyword | CMOS,wideband amplifier,transformer,power amplifier,low noise amplifier,switchless bidirectional amplifier,Ka band,SPDT,W band,D band, | en |
| dc.relation.page | 178 | - |
| dc.identifier.doi | 10.6342/NTU202400019 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-01-05 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電信工程學研究所 | - |
| 顯示於系所單位： | 電信工程學研究所 | |
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