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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91385| Title: | 使用無須頻率補償之二級放大器實作的導管式循序漸進式類比數位轉換器 A Pipelined-SAR ADC with Compensation-Free Two-Stage OPAMP |
| Authors: | 黃士杰 Shih-Jie Huang |
| Advisor: | 李泰成 Tai-Cheng Lee |
| Keyword: | 二級放大器,環形放大器,無須頻率補償,導管式循序漸進式類比數位轉換器,平行轉換, Two-Stage Amplifier,Ring Amplifier,Frequency-Compensation-Free,Pipelined-SAR Analog-to-Digital Converters,Parallel Conversion, |
| Publication Year : | 2023 |
| Degree: | 碩士 |
| Abstract: | 本篇論文提出一個無須補償之兩級放大器，相較於傳統放大器，除了無須補償電容之外，其具有高迴轉率以及開關控制，使其具高速和低功耗的優點。此放大器被應用在導管式-循序漸進式類比數位轉換器中。此外，提出的轉換器使用平行比較架構，加速其運算，以此達成十億赫茲的取樣頻率。
本晶片使用台積電28奈米製程下線，總面積為1.00平方毫米。量測中，在十億赫茲的取樣頻率下，可測得52.01分貝的訊號對雜訊失真比，同時僅消耗7.99毫瓦。 A compensation-free two-stage amplifier is proposed in this thesis. Compared to traditional operational amplifiers, the compensation capacitor can be omitted. Also, the proposed amplifier has high slew rate and can be turned off when idle, leading to its high-speed and low-power feature. This amplifier is adopted in a pipelined-SAR ADC, where parallel conversion architecture is applied to accelerate the conversion rate to reach a sampling rate of 1 GS/s. The chip is fabricated with 28 nm process. The total area is 1.00 mm2. In measurement, under sampling rate of 1 GS/s, the proposed ADC has an SNDR of 52.01 dB and consumes 7.99 mW. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91385 |
| DOI: | 10.6342/NTU202400074 |
| Fulltext Rights: | 同意授權(限校園內公開) |
| Appears in Collections: | 電子工程學研究所 |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-112-1.pdf Access limited in NTU ip range | 8.2 MB | Adobe PDF |
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