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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8993
標題: | 晶片上多核處理器與其驗證模型之設計 Design of On-chip Multi-Processor and its Verification Model |
作者: | Guang-Huei Lin 林光輝 |
指導教授: | 陳少傑(Sao-Jie Chen) |
關鍵字: | 晶片上系統,多核,處理器, SoC,Multi-core,Processor, |
出版年 : | 2009 |
學位: | 博士 |
摘要: | 這論文是一個研究專案的成果,旨在開發嵌入式多媒體系統使用的晶片上多核處理器架構。近年來晶片上多核處理器已經成為數位電路設計,計算機輔助設計,以及嵌入式系統開發的焦點。我們的重點是設計一種新型的基於PLX的單指令多資料指令集架構的晶片設計平台。本論文探討研究成果的幾個面向,包含各種單處理器與多處理器的微架構,系統層級軟硬體協同設計和協同驗證,以及平行化的方法。 This Dissertation is the outcomes of a research project aiming at developing multi-processor System-on-Chip (SoC) architecture for embedded multimedia systems. Since its inception a decade ago, SoC has captured the attentions of application specific integrated circuit (ASIC) design houses, computer aided design (CAD) companies, and embedded system developers. In particular, the immense popularity of killer multimedia gadgets, such as the iPod and smart phone, has fueled unprecedented interests in developing new generation multimedia SoC systems. We focused on the design of a novel SoC platform based on a PLX Subword-Parallel Single Instruction Multiple Data (SWP-SIMD) instruction set architecture. Most of the materials included in this Dissertation are drawn from the outcomes of our research project. Several single-processor and multi-processor micro-architectures are deeply studied and adapted to our design. However, the high level of integration also brings great challenges to system designers. Hardware and software are necessarily becoming convergent and must be fully concurrent design endeavors. The system level hardware/software co-design and co-verification methodologies are also discussed in this Dissertation. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/8993 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電機工程學系 |
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